radeonsi: use conformant line rasterization

[mesa.git] / src / gallium / drivers / radeon / cayman_msaa.c

diff --git a/src/gallium/drivers/radeon/cayman_msaa.c b/src/gallium/drivers/radeon/cayman_msaa.c
index 9412e8962c4c77b12f8dbe9cb6e87adfd26028e4..89c4937a2cc684e97213cd57cb2d182a4d4efad5 100644 (file)
--- a/src/gallium/drivers/radeon/cayman_msaa.c
+++ b/src/gallium/drivers/radeon/cayman_msaa.c
@@ -195,10 +195,19 @@ void cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples)
 }
 
 void cayman_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
-                            int ps_iter_samples, int overrast_samples)
+                            int ps_iter_samples, int overrast_samples,
+                            unsigned sc_mode_cntl_1)
 {
        int setup_samples = nr_samples > 1 ? nr_samples :
                            overrast_samples > 1 ? overrast_samples : 0;
+       /* Required by OpenGL line rasterization.
+        *
+        * TODO: We should also enable perpendicular endcaps for AA lines,
+        *       but that requires implementing line stippling in the pixel
+        *       shader. SC can only do line stippling with axis-aligned
+        *       endcaps.
+        */
+       unsigned sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
 
        if (setup_samples > 1) {
                /* indexed by log2(nr_samples) */
@@ -214,7 +223,7 @@ void cayman_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
                        util_logbase2(util_next_power_of_two(ps_iter_samples));
 
                radeon_set_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
-               radeon_emit(cs, S_028BDC_LAST_PIXEL(1) |
+               radeon_emit(cs, sc_line_cntl |
                            S_028BDC_EXPAND_LINE_WIDTH(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
                radeon_emit(cs, S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
                            S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
@@ -230,27 +239,24 @@ void cayman_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
                                               S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
                        radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
                                               EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1) |
-                                              EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
-                                              EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
+                                              sc_mode_cntl_1);
                } else if (overrast_samples > 1) {
                        radeon_set_context_reg(cs, CM_R_028804_DB_EQAA,
                                               S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
                                               S_028804_STATIC_ANCHOR_ASSOCIATIONS(1) |
                                               S_028804_OVERRASTERIZATION_AMOUNT(log_samples));
                        radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
-                                              EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
-                                              EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
+                                              sc_mode_cntl_1);
                }
        } else {
                radeon_set_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
-               radeon_emit(cs, S_028BDC_LAST_PIXEL(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
+               radeon_emit(cs, sc_line_cntl); /* CM_R_028BDC_PA_SC_LINE_CNTL */
                radeon_emit(cs, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
 
                radeon_set_context_reg(cs, CM_R_028804_DB_EQAA,
                                       S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
                                       S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
                radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
-                                      EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
-                                      EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
+                                      sc_mode_cntl_1);
        }
 }