radeonsi: add support for Mullins asics.

[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.c

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c b/src/gallium/drivers/radeon/r600_pipe_common.c
index 92f43deba54ecd6c5a307ac0992278e451e2f232..70c4d1adefba783b553af0e6ff1dfc60b7fd3e9f 100644 (file)
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -45,7 +45,7 @@ void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw)
        num_dw += ctx->rings.dma.cs->cdw;
        /* Flush if there's not enough space. */
        if (num_dw > RADEON_MAX_CMDBUF_DWORDS) {
-               ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC);
+               ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
        }
 }
 
@@ -53,7 +53,71 @@ static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
 {
 }
 
-static void r600_flush_dma_ring(void *ctx, unsigned flags)
+void r600_preflush_suspend_features(struct r600_common_context *ctx)
+{
+       /* Disable render condition. */
+       ctx->saved_render_cond = NULL;
+       ctx->saved_render_cond_cond = FALSE;
+       ctx->saved_render_cond_mode = 0;
+       if (ctx->current_render_cond) {
+               ctx->saved_render_cond = ctx->current_render_cond;
+               ctx->saved_render_cond_cond = ctx->current_render_cond_cond;
+               ctx->saved_render_cond_mode = ctx->current_render_cond_mode;
+               ctx->b.render_condition(&ctx->b, NULL, FALSE, 0);
+       }
+
+       /* suspend queries */
+       ctx->nontimer_queries_suspended = false;
+       if (ctx->num_cs_dw_nontimer_queries_suspend) {
+               r600_suspend_nontimer_queries(ctx);
+               ctx->nontimer_queries_suspended = true;
+       }
+
+       ctx->streamout.suspended = false;
+       if (ctx->streamout.begin_emitted) {
+               r600_emit_streamout_end(ctx);
+               ctx->streamout.suspended = true;
+       }
+}
+
+void r600_postflush_resume_features(struct r600_common_context *ctx)
+{
+       if (ctx->streamout.suspended) {
+               ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
+               r600_streamout_buffers_dirty(ctx);
+       }
+
+       /* resume queries */
+       if (ctx->nontimer_queries_suspended) {
+               r600_resume_nontimer_queries(ctx);
+       }
+
+       /* Re-enable render condition. */
+       if (ctx->saved_render_cond) {
+               ctx->b.render_condition(&ctx->b, ctx->saved_render_cond,
+                                         ctx->saved_render_cond_cond,
+                                         ctx->saved_render_cond_mode);
+       }
+}
+
+static void r600_flush_from_st(struct pipe_context *ctx,
+                              struct pipe_fence_handle **fence,
+                              unsigned flags)
+{
+       struct r600_common_context *rctx = (struct r600_common_context *)ctx;
+       unsigned rflags = 0;
+
+       if (flags & PIPE_FLUSH_END_OF_FRAME)
+               rflags |= RADEON_FLUSH_END_OF_FRAME;
+
+       if (rctx->rings.dma.cs) {
+               rctx->rings.dma.flush(rctx, rflags, NULL);
+       }
+       rctx->rings.gfx.flush(rctx, rflags, fence);
+}
+
+static void r600_flush_dma_ring(void *ctx, unsigned flags,
+                               struct pipe_fence_handle **fence)
 {
        struct r600_common_context *rctx = (struct r600_common_context *)ctx;
        struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
@@ -63,7 +127,7 @@ static void r600_flush_dma_ring(void *ctx, unsigned flags)
        }
 
        rctx->rings.dma.flushing = true;
-       rctx->ws->cs_flush(cs, flags, 0);
+       rctx->ws->cs_flush(cs, flags, fence, 0);
        rctx->rings.dma.flushing = false;
 }
 
@@ -85,6 +149,7 @@ bool r600_common_context_init(struct r600_common_context *rctx,
        rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
        rctx->b.transfer_inline_write = u_default_transfer_inline_write;
         rctx->b.memory_barrier = r600_memory_barrier;
+       rctx->b.flush = r600_flush_from_st;
 
        r600_init_context_texture_functions(rctx);
        r600_streamout_init(rctx);
@@ -228,6 +293,7 @@ static const char* r600_get_name(struct pipe_screen* pscreen)
        case CHIP_KAVERI: return "AMD KAVERI";
        case CHIP_KABINI: return "AMD KABINI";
        case CHIP_HAWAII: return "AMD HAWAII";
+       case CHIP_MULLINS: return "AMD MULLINS";
        default: return "AMD unknown";
        }
 }
@@ -345,6 +411,12 @@ const char *r600_get_llvm_processor_name(enum radeon_family family)
        case CHIP_KABINI: return "kabini";
        case CHIP_KAVERI: return "kaveri";
        case CHIP_HAWAII: return "hawaii";
+       case CHIP_MULLINS:
+#if HAVE_LLVM >= 0x0305
+               return "mullins";
+#else
+               return "kabini";
+#endif
        default: return "";
 #endif
        }
@@ -440,6 +512,13 @@ static int r600_get_compute_param(struct pipe_screen *screen,
                }
                return sizeof(uint64_t);
 
+       case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
+               if (ret) {
+                       uint32_t *max_clock_frequency = ret;
+                       *max_clock_frequency = rscreen->info.max_sclk;
+               }
+               return sizeof(uint32_t);
+
        default:
                fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
                return 0;