gallium/radeon: get pipe_interleave_bytes AKA group_bytes from the winsys
[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.c
index e0c2469747e35cebc70d1a2e59fedabba235ca5c..977c5d0d71d0ede78d07b0f4bd454d3d53c037de 100644 (file)
@@ -800,84 +800,6 @@ static boolean r600_fence_finish(struct pipe_screen *screen,
        return rws->fence_wait(rws, rfence->gfx, timeout);
 }
 
-static bool r600_interpret_tiling(struct r600_common_screen *rscreen,
-                                 uint32_t tiling_config)
-{
-       switch ((tiling_config & 0x30) >> 4) {
-       case 0:
-               rscreen->tiling_info.num_banks = 4;
-               break;
-       case 1:
-               rscreen->tiling_info.num_banks = 8;
-               break;
-       default:
-               return false;
-
-       }
-       switch ((tiling_config & 0xc0) >> 6) {
-       case 0:
-               rscreen->tiling_info.group_bytes = 256;
-               break;
-       case 1:
-               rscreen->tiling_info.group_bytes = 512;
-               break;
-       default:
-               return false;
-       }
-       return true;
-}
-
-static bool evergreen_interpret_tiling(struct r600_common_screen *rscreen,
-                                      uint32_t tiling_config)
-{
-       switch ((tiling_config & 0xf0) >> 4) {
-       case 0:
-               rscreen->tiling_info.num_banks = 4;
-               break;
-       case 1:
-               rscreen->tiling_info.num_banks = 8;
-               break;
-       case 2:
-               rscreen->tiling_info.num_banks = 16;
-               break;
-       default:
-               return false;
-       }
-
-       switch ((tiling_config & 0xf00) >> 8) {
-       case 0:
-               rscreen->tiling_info.group_bytes = 256;
-               break;
-       case 1:
-               rscreen->tiling_info.group_bytes = 512;
-               break;
-       default:
-               return false;
-       }
-       return true;
-}
-
-static bool r600_init_tiling(struct r600_common_screen *rscreen)
-{
-       uint32_t tiling_config = rscreen->info.r600_tiling_config;
-
-       /* set default group bytes, overridden by tiling info ioctl */
-       if (rscreen->chip_class <= R700) {
-               rscreen->tiling_info.group_bytes = 256;
-       } else {
-               rscreen->tiling_info.group_bytes = 512;
-       }
-
-       if (!tiling_config)
-               return true;
-
-       if (rscreen->chip_class <= R700) {
-               return r600_interpret_tiling(rscreen, tiling_config);
-       } else {
-               return evergreen_interpret_tiling(rscreen, tiling_config);
-       }
-}
-
 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
                                                  const struct pipe_resource *templ)
 {
@@ -934,9 +856,6 @@ bool r600_common_screen_init(struct r600_common_screen *rscreen,
        rscreen->chip_class = rscreen->info.chip_class;
        rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
 
-       if (!r600_init_tiling(rscreen)) {
-               return false;
-       }
        util_format_s3tc_init();
        pipe_mutex_init(rscreen->aux_context_lock);
        pipe_mutex_init(rscreen->gpu_load_mutex);
@@ -981,8 +900,10 @@ bool r600_common_screen_init(struct r600_common_screen *rscreen,
                printf("r600_gb_backend_map = %i\n", rscreen->info.r600_gb_backend_map);
                printf("r600_gb_backend_map_valid = %i\n", rscreen->info.r600_gb_backend_map_valid);
                printf("r600_tiling_config = 0x%x\n", rscreen->info.r600_tiling_config);
+               printf("r600_num_banks = %i\n", rscreen->info.r600_num_banks);
                printf("num_render_backends = %i\n", rscreen->info.num_render_backends);
                printf("num_tile_pipes = %i\n", rscreen->info.num_tile_pipes);
+               printf("pipe_interleave_bytes = %i\n", rscreen->info.pipe_interleave_bytes);
                printf("si_tile_mode_array_valid = %i\n", rscreen->info.si_tile_mode_array_valid);
                printf("cik_macrotile_mode_array_valid = %i\n", rscreen->info.cik_macrotile_mode_array_valid);
        }