#include <inttypes.h>
#include <sys/utsname.h>
-#ifndef HAVE_LLVM
-#define HAVE_LLVM 0
-#endif
-
-#if HAVE_LLVM
#include <llvm-c/TargetMachine.h>
-#endif
-#ifndef MESA_LLVM_VERSION_PATCH
-#define MESA_LLVM_VERSION_PATCH 0
-#endif
struct r600_multi_fence {
struct pipe_reference reference;
/*
* shader binary helpers.
*/
-void radeon_shader_binary_init(struct ac_shader_binary *b)
+void si_radeon_shader_binary_init(struct ac_shader_binary *b)
{
memset(b, 0, sizeof(*b));
}
-void radeon_shader_binary_clean(struct ac_shader_binary *b)
+void si_radeon_shader_binary_clean(struct ac_shader_binary *b)
{
if (!b)
return;
* \param old_value Previous fence value (for a bug workaround)
* \param new_value Fence value to write for this event.
*/
-void r600_gfx_write_event_eop(struct r600_common_context *ctx,
- unsigned event, unsigned event_flags,
- unsigned data_sel,
- struct r600_resource *buf, uint64_t va,
- uint32_t old_fence, uint32_t new_fence,
- unsigned query_type)
+void si_gfx_write_event_eop(struct r600_common_context *ctx,
+ unsigned event, unsigned event_flags,
+ unsigned data_sel,
+ struct r600_resource *buf, uint64_t va,
+ uint32_t new_fence, unsigned query_type)
{
struct radeon_winsys_cs *cs = ctx->gfx.cs;
unsigned op = EVENT_TYPE(event) |
EVENT_INDEX(5) |
event_flags;
+ unsigned sel = EOP_DATA_SEL(data_sel);
+
+ /* Wait for write confirmation before writing data, but don't send
+ * an interrupt. */
+ if (ctx->chip_class >= SI && data_sel != EOP_DATA_SEL_DISCARD)
+ sel |= EOP_INT_SEL(EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM);
if (ctx->chip_class >= GFX9) {
/* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
*/
if (ctx->chip_class == GFX9 &&
query_type != PIPE_QUERY_OCCLUSION_COUNTER &&
- query_type != PIPE_QUERY_OCCLUSION_PREDICATE) {
+ query_type != PIPE_QUERY_OCCLUSION_PREDICATE &&
+ query_type != PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE) {
struct r600_resource *scratch = ctx->eop_bug_scratch;
assert(16 * ctx->screen->info.num_render_backends <=
radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, 6, 0));
radeon_emit(cs, op);
- radeon_emit(cs, EOP_DATA_SEL(data_sel));
+ radeon_emit(cs, sel);
radeon_emit(cs, va); /* address lo */
radeon_emit(cs, va >> 32); /* address hi */
radeon_emit(cs, new_fence); /* immediate data lo */
} else {
if (ctx->chip_class == CIK ||
ctx->chip_class == VI) {
+ struct r600_resource *scratch = ctx->eop_bug_scratch;
+ uint64_t va = scratch->gpu_address;
+
/* Two EOP events are required to make all engines go idle
* (and optional cache flushes executed) before the timestamp
* is written.
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
radeon_emit(cs, op);
radeon_emit(cs, va);
- radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
- radeon_emit(cs, old_fence); /* immediate data */
+ radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
+ radeon_emit(cs, 0); /* immediate data */
radeon_emit(cs, 0); /* unused */
+
+ radeon_add_to_buffer_list(ctx, &ctx->gfx, scratch,
+ RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
}
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
radeon_emit(cs, op);
radeon_emit(cs, va);
- radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
+ radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
radeon_emit(cs, new_fence); /* immediate data */
radeon_emit(cs, 0); /* unused */
}
RADEON_PRIO_QUERY);
}
-unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen)
+unsigned si_gfx_write_fence_dwords(struct r600_common_screen *screen)
{
unsigned dwords = 6;
return dwords;
}
-void r600_gfx_wait_fence(struct r600_common_context *ctx,
- uint64_t va, uint32_t ref, uint32_t mask)
+void si_gfx_wait_fence(struct r600_common_context *ctx,
+ uint64_t va, uint32_t ref, uint32_t mask)
{
struct radeon_winsys_cs *cs = ctx->gfx.cs;
radeon_emit(cs, 4); /* poll interval */
}
-void r600_draw_rectangle(struct blitter_context *blitter,
- int x1, int y1, int x2, int y2, float depth,
- enum blitter_attrib_type type,
- const union pipe_color_union *attrib)
+void si_draw_rectangle(struct blitter_context *blitter,
+ int x1, int y1, int x2, int y2,
+ float depth, unsigned num_instances,
+ enum blitter_attrib_type type,
+ const union blitter_attrib *attrib)
{
struct r600_common_context *rctx =
(struct r600_common_context*)util_blitter_get_pipe(blitter);
unsigned offset = 0;
float *vb;
- if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
- util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
- return;
- }
-
/* Some operations (like color resolve on r6xx) don't work
* with the conventional primitive types.
* One that works is PT_RECTLIST, which we use here. */
rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
/* Upload vertices. The hw rectangle has only 3 vertices,
- * I guess the 4th one is derived from the first 3.
+ * The 4th one is derived from the first 3.
* The vertex specification should match u_blitter's vertex element state. */
u_upload_alloc(rctx->b.stream_uploader, 0, sizeof(float) * 24,
rctx->screen->info.tcc_cache_line_size,
vb[18] = depth;
vb[19] = 1;
- if (attrib) {
- memcpy(vb+4, attrib->f, sizeof(float)*4);
- memcpy(vb+12, attrib->f, sizeof(float)*4);
- memcpy(vb+20, attrib->f, sizeof(float)*4);
+ switch (type) {
+ case UTIL_BLITTER_ATTRIB_COLOR:
+ memcpy(vb+4, attrib->color, sizeof(float)*4);
+ memcpy(vb+12, attrib->color, sizeof(float)*4);
+ memcpy(vb+20, attrib->color, sizeof(float)*4);
+ break;
+ case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
+ case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
+ vb[6] = vb[14] = vb[22] = attrib->texcoord.z;
+ vb[7] = vb[15] = vb[23] = attrib->texcoord.w;
+ /* fall through */
+ vb[4] = attrib->texcoord.x1;
+ vb[5] = attrib->texcoord.y1;
+ vb[12] = attrib->texcoord.x1;
+ vb[13] = attrib->texcoord.y2;
+ vb[20] = attrib->texcoord.x2;
+ vb[21] = attrib->texcoord.y1;
+ break;
+ default:; /* Nothing to do. */
}
/* draw */
- util_draw_vertex_buffer(&rctx->b, NULL, buf, blitter->vb_slot, offset,
- R600_PRIM_RECTANGLE_LIST, 3, 2);
+ struct pipe_vertex_buffer vbuffer = {};
+ vbuffer.buffer.resource = buf;
+ vbuffer.stride = 2 * 4 * sizeof(float); /* vertex size */
+ vbuffer.buffer_offset = offset;
+
+ rctx->b.set_vertex_buffers(&rctx->b, blitter->vb_slot, 1, &vbuffer);
+ util_draw_arrays_instanced(&rctx->b, R600_PRIM_RECTANGLE_LIST, 0, 3,
+ 0, num_instances);
pipe_resource_reference(&buf, NULL);
}
}
}
-void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
- struct r600_resource *dst, struct r600_resource *src)
+void si_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
+ struct r600_resource *dst, struct r600_resource *src)
{
uint64_t vram = ctx->dma.cs->used_vram;
uint64_t gtt = ctx->dma.cs->used_gart;
{
}
-void r600_preflush_suspend_features(struct r600_common_context *ctx)
+void si_preflush_suspend_features(struct r600_common_context *ctx)
{
/* suspend queries */
if (!LIST_IS_EMPTY(&ctx->active_queries))
- r600_suspend_queries(ctx);
+ si_suspend_queries(ctx);
ctx->streamout.suspended = false;
if (ctx->streamout.begin_emitted) {
- r600_emit_streamout_end(ctx);
+ si_emit_streamout_end(ctx);
ctx->streamout.suspended = true;
}
}
-void r600_postflush_resume_features(struct r600_common_context *ctx)
+void si_postflush_resume_features(struct r600_common_context *ctx)
{
if (ctx->streamout.suspended) {
ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
- r600_streamout_buffers_dirty(ctx);
+ si_streamout_buffers_dirty(ctx);
}
/* resume queries */
if (!LIST_IS_EMPTY(&ctx->active_queries))
- r600_resume_queries(ctx);
+ si_resume_queries(ctx);
+}
+
+static void r600_add_fence_dependency(struct r600_common_context *rctx,
+ struct pipe_fence_handle *fence)
+{
+ struct radeon_winsys *ws = rctx->ws;
+
+ if (rctx->dma.cs)
+ ws->cs_add_fence_dependency(rctx->dma.cs, fence);
+ ws->cs_add_fence_dependency(rctx->gfx.cs, fence);
+}
+
+static void r600_fence_server_sync(struct pipe_context *ctx,
+ struct pipe_fence_handle *fence)
+{
+ struct r600_common_context *rctx = (struct r600_common_context *)ctx;
+ struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
+
+ /* Only amdgpu needs to handle fence dependencies (for fence imports).
+ * radeon synchronizes all rings by default and will not implement
+ * fence imports.
+ */
+ if (rctx->screen->info.drm_major == 2)
+ return;
+
+ /* Only imported fences need to be handled by fence_server_sync,
+ * because the winsys handles synchronizations automatically for BOs
+ * within the process.
+ *
+ * Simply skip unflushed fences here, and the winsys will drop no-op
+ * dependencies (i.e. dependencies within the same ring).
+ */
+ if (rfence->gfx_unflushed.ctx)
+ return;
+
+ /* All unflushed commands will not start execution before
+ * this fence dependency is signalled.
+ *
+ * Should we flush the context to allow more GPU parallelism?
+ */
+ if (rfence->sdma)
+ r600_add_fence_dependency(rctx, rfence->sdma);
+ if (rfence->gfx)
+ r600_add_fence_dependency(rctx, rfence->gfx);
}
static void r600_flush_from_st(struct pipe_context *ctx,
if (fence) {
struct r600_multi_fence *multi_fence =
CALLOC_STRUCT(r600_multi_fence);
- if (!multi_fence)
- return;
+ if (!multi_fence) {
+ ws->fence_reference(&sdma_fence, NULL);
+ ws->fence_reference(&gfx_fence, NULL);
+ goto finish;
+ }
multi_fence->reference.count = 1;
/* If both fences are NULL, fence_finish will always return true. */
screen->fence_reference(screen, fence, NULL);
*fence = (struct pipe_fence_handle*)multi_fence;
}
-
+finish:
if (!(flags & PIPE_FLUSH_DEFERRED)) {
if (rctx->dma.cs)
ws->cs_sync_flush(rctx->dma.cs);
}
if (check_vm)
- radeon_save_cs(rctx->ws, cs, &saved, true);
+ si_save_cs(rctx->ws, cs, &saved, true);
rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence);
if (fence)
rctx->ws->fence_wait(rctx->ws, rctx->last_sdma_fence, 800*1000*1000);
rctx->check_vm_faults(rctx, &saved, RING_DMA);
- radeon_clear_saved_cs(&saved);
+ si_clear_saved_cs(&saved);
}
}
* Store a linearized copy of all chunks of \p cs together with the buffer
* list in \p saved.
*/
-void radeon_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
- struct radeon_saved_cs *saved, bool get_buffer_list)
+void si_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
+ struct radeon_saved_cs *saved, bool get_buffer_list)
{
- void *buf;
+ uint32_t *buf;
unsigned i;
/* Save the IB chunks. */
memset(saved, 0, sizeof(*saved));
}
-void radeon_clear_saved_cs(struct radeon_saved_cs *saved)
+void si_clear_saved_cs(struct radeon_saved_cs *saved)
{
FREE(saved->ib);
FREE(saved->bo_list);
sizeof(rctx->device_reset_callback));
}
-bool r600_check_device_reset(struct r600_common_context *rctx)
+bool si_check_device_reset(struct r600_common_context *rctx)
{
enum pipe_reset_status status;
return ctx->ws->buffer_commit(res->buf, box->x, box->width, commit);
}
-bool r600_common_context_init(struct r600_common_context *rctx,
- struct r600_common_screen *rscreen,
- unsigned context_flags)
+bool si_common_context_init(struct r600_common_context *rctx,
+ struct r600_common_screen *rscreen,
+ unsigned context_flags)
{
slab_create_child(&rctx->pool_transfers, &rscreen->pool_transfers);
slab_create_child(&rctx->pool_transfers_unsync, &rscreen->pool_transfers);
rctx->family = rscreen->family;
rctx->chip_class = rscreen->chip_class;
- rctx->b.invalidate_resource = r600_invalidate_resource;
+ rctx->b.invalidate_resource = si_invalidate_resource;
rctx->b.resource_commit = r600_resource_commit;
rctx->b.transfer_map = u_transfer_map_vtbl;
rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
rctx->b.memory_barrier = r600_memory_barrier;
rctx->b.flush = r600_flush_from_st;
rctx->b.set_debug_callback = r600_set_debug_callback;
+ rctx->b.fence_server_sync = r600_fence_server_sync;
rctx->dma_clear_buffer = r600_dma_clear_buffer_fallback;
+ rctx->b.buffer_subdata = si_buffer_subdata;
- /* evergreen_compute.c has a special codepath for global buffers.
- * Everything else can use the direct path.
- */
- if ((rscreen->chip_class == EVERGREEN || rscreen->chip_class == CAYMAN) &&
- (context_flags & PIPE_CONTEXT_COMPUTE_ONLY))
- rctx->b.buffer_subdata = u_default_buffer_subdata;
- else
- rctx->b.buffer_subdata = r600_buffer_subdata;
+ /* Set a reasonable default to avoid a performance regression in r600
+ * on stable branches. */
+ rctx->current_rast_prim = PIPE_PRIM_TRIANGLES;
if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
rctx->b.get_device_reset_status = r600_get_reset_status;
rctx->b.set_device_reset_callback = r600_set_device_reset_callback;
- r600_init_context_texture_functions(rctx);
- r600_init_viewport_functions(rctx);
- r600_streamout_init(rctx);
- r600_query_init(rctx);
- cayman_init_msaa(&rctx->b);
+ si_init_context_texture_functions(rctx);
+ si_streamout_init(rctx);
+ si_init_query_functions(rctx);
+ si_init_msaa(&rctx->b);
- if (rctx->chip_class == GFX9) {
+ if (rctx->chip_class == CIK ||
+ rctx->chip_class == VI ||
+ rctx->chip_class == GFX9) {
rctx->eop_bug_scratch = (struct r600_resource*)
pipe_buffer_create(&rscreen->b, 0, PIPE_USAGE_DEFAULT,
16 * rscreen->info.num_render_backends);
return true;
}
-void r600_common_context_cleanup(struct r600_common_context *rctx)
+void si_common_context_cleanup(struct r600_common_context *rctx)
{
unsigned i,j;
{ "norbplus", DBG_NO_RB_PLUS, "Disable RB+." },
{ "sisched", DBG_SI_SCHED, "Enable LLVM SI Machine Instruction Scheduler." },
{ "mono", DBG_MONOLITHIC_SHADERS, "Use old-style monolithic shaders compiled on demand" },
- { "ce", DBG_CE, "Force enable the constant engine" },
- { "noce", DBG_NO_CE, "Disable the constant engine"},
{ "unsafemath", DBG_UNSAFE_MATH, "Enable unsafe math shader optimizations" },
{ "nodccfb", DBG_NO_DCC_FB, "Disable separate DCC on the main framebuffer" },
+ { "nodpbb", DBG_NO_DPBB, "Disable DPBB." },
+ { "nodfsm", DBG_NO_DFSM, "Disable DFSM." },
+ { "nooutoforder", DBG_NO_OUT_OF_ORDER, "Disable out-of-order rasterization" },
DEBUG_NAMED_VALUE_END /* must be last */
};
static void r600_disk_cache_create(struct r600_common_screen *rscreen)
{
/* Don't use the cache if shader dumping is enabled. */
- if (rscreen->debug_flags &
- (DBG_FS | DBG_VS | DBG_TCS | DBG_TES | DBG_GS | DBG_PS | DBG_CS))
+ if (rscreen->debug_flags & DBG_ALL_SHADERS)
return;
uint32_t mesa_timestamp;
&mesa_timestamp)) {
char *timestamp_str;
int res = -1;
- if (rscreen->chip_class < SI) {
- res = asprintf(×tamp_str, "%u",mesa_timestamp);
- }
-#if HAVE_LLVM
- else {
- uint32_t llvm_timestamp;
- if (disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo,
- &llvm_timestamp)) {
- res = asprintf(×tamp_str, "%u_%u",
- mesa_timestamp, llvm_timestamp);
- }
+ uint32_t llvm_timestamp;
+
+ if (disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo,
+ &llvm_timestamp)) {
+ res = asprintf(×tamp_str, "%u_%u",
+ mesa_timestamp, llvm_timestamp);
}
-#endif
+
if (res != -1) {
/* These flags affect shader compilation. */
uint64_t shader_debug_flags =
static float r600_get_paramf(struct pipe_screen* pscreen,
enum pipe_capf param)
{
- struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
-
switch (param) {
case PIPE_CAPF_MAX_LINE_WIDTH:
case PIPE_CAPF_MAX_LINE_WIDTH_AA:
case PIPE_CAPF_MAX_POINT_WIDTH:
case PIPE_CAPF_MAX_POINT_WIDTH_AA:
- if (rscreen->family >= CHIP_CEDAR)
- return 16384.0f;
- else
- return 8192.0f;
+ return 8192.0f;
case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
return 16.0f;
case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
}
}
-const char *r600_get_llvm_processor_name(enum radeon_family family)
+const char *si_get_llvm_processor_name(enum radeon_family family)
{
switch (family) {
case CHIP_R600:
/* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
* round number.
*/
- if (screen->chip_class >= SI)
- return 2048;
-
- return 256;
+ return 2048;
}
static int r600_get_compute_param(struct pipe_screen *screen,
* GPUs, so we need to use the name of a similar GPU.
*/
default:
- gpu = r600_get_llvm_processor_name(rscreen->family);
+ gpu = si_get_llvm_processor_name(rscreen->family);
break;
}
if (ret) {
case PIPE_COMPUTE_CAP_ADDRESS_BITS:
if (ret) {
uint32_t *address_bits = ret;
- address_bits[0] = 32;
- if (rscreen->chip_class >= SI)
- address_bits[0] = 64;
+ address_bits[0] = 64;
}
return 1 * sizeof(uint32_t);
case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
if (ret) {
uint64_t *max_variable_threads_per_block = ret;
- if (rscreen->chip_class >= SI &&
- ir_type == PIPE_SHADER_IR_TGSI)
+ if (ir_type == PIPE_SHADER_IR_TGSI)
*max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
else
*max_variable_threads_per_block = 0;
info->nr_device_memory_evictions = info->device_memory_evicted / 64;
}
-struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
- const struct pipe_resource *templ)
+struct pipe_resource *si_resource_create_common(struct pipe_screen *screen,
+ const struct pipe_resource *templ)
{
if (templ->target == PIPE_BUFFER) {
- return r600_buffer_create(screen, templ, 256);
+ return si_buffer_create(screen, templ, 256);
} else {
- return r600_texture_create(screen, templ);
+ return si_texture_create(screen, templ);
}
}
-bool r600_common_screen_init(struct r600_common_screen *rscreen,
- struct radeon_winsys *ws)
+bool si_common_screen_init(struct r600_common_screen *rscreen,
+ struct radeon_winsys *ws)
{
char family_name[32] = {}, llvm_string[32] = {}, kernel_version[128] = {};
struct utsname uname_data;
rscreen->b.fence_finish = r600_fence_finish;
rscreen->b.fence_reference = r600_fence_reference;
rscreen->b.resource_destroy = u_resource_destroy_vtbl;
- rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
+ rscreen->b.resource_from_user_memory = si_buffer_from_user_memory;
rscreen->b.query_memory_info = r600_query_memory_info;
if (rscreen->info.has_hw_decode) {
- rscreen->b.get_video_param = rvid_get_video_param;
- rscreen->b.is_video_format_supported = rvid_is_format_supported;
+ rscreen->b.get_video_param = si_vid_get_video_param;
+ rscreen->b.is_video_format_supported = si_vid_is_format_supported;
} else {
rscreen->b.get_video_param = r600_get_video_param;
rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
}
- r600_init_screen_texture_functions(rscreen);
- r600_init_screen_query_functions(rscreen);
+ si_init_screen_texture_functions(rscreen);
+ si_init_screen_query_functions(rscreen);
rscreen->family = rscreen->info.family;
rscreen->chip_class = rscreen->info.chip_class;
printf("uvd_fw_version = %u\n", rscreen->info.uvd_fw_version);
printf("vce_fw_version = %u\n", rscreen->info.vce_fw_version);
printf("me_fw_version = %i\n", rscreen->info.me_fw_version);
+ printf("me_fw_feature = %i\n", rscreen->info.me_fw_feature);
printf("pfp_fw_version = %i\n", rscreen->info.pfp_fw_version);
+ printf("pfp_fw_feature = %i\n", rscreen->info.pfp_fw_feature);
printf("ce_fw_version = %i\n", rscreen->info.ce_fw_version);
+ printf("ce_fw_feature = %i\n", rscreen->info.ce_fw_feature);
printf("vce_harvest_config = %i\n", rscreen->info.vce_harvest_config);
printf("clock_crystal_freq = %i\n", rscreen->info.clock_crystal_freq);
printf("tcc_cache_line_size = %u\n", rscreen->info.tcc_cache_line_size);
return true;
}
-void r600_destroy_common_screen(struct r600_common_screen *rscreen)
+void si_destroy_common_screen(struct r600_common_screen *rscreen)
{
- r600_perfcounters_destroy(rscreen);
- r600_gpu_load_kill_thread(rscreen);
+ si_perfcounters_destroy(rscreen);
+ si_gpu_load_kill_thread(rscreen);
mtx_destroy(&rscreen->gpu_load_mutex);
mtx_destroy(&rscreen->aux_context_lock);
FREE(rscreen);
}
-bool r600_can_dump_shader(struct r600_common_screen *rscreen,
- unsigned processor)
+bool si_can_dump_shader(struct r600_common_screen *rscreen,
+ unsigned processor)
{
- switch (processor) {
- case PIPE_SHADER_VERTEX:
- return (rscreen->debug_flags & DBG_VS) != 0;
- case PIPE_SHADER_TESS_CTRL:
- return (rscreen->debug_flags & DBG_TCS) != 0;
- case PIPE_SHADER_TESS_EVAL:
- return (rscreen->debug_flags & DBG_TES) != 0;
- case PIPE_SHADER_GEOMETRY:
- return (rscreen->debug_flags & DBG_GS) != 0;
- case PIPE_SHADER_FRAGMENT:
- return (rscreen->debug_flags & DBG_PS) != 0;
- case PIPE_SHADER_COMPUTE:
- return (rscreen->debug_flags & DBG_CS) != 0;
- default:
- return false;
- }
+ return rscreen->debug_flags & (1 << processor);
}
-bool r600_extra_shader_checks(struct r600_common_screen *rscreen, unsigned processor)
+bool si_extra_shader_checks(struct r600_common_screen *rscreen, unsigned processor)
{
return (rscreen->debug_flags & DBG_CHECK_IR) ||
- r600_can_dump_shader(rscreen, processor);
+ si_can_dump_shader(rscreen, processor);
}
-void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
- uint64_t offset, uint64_t size, unsigned value)
+void si_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
+ uint64_t offset, uint64_t size, unsigned value)
{
struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
projects / mesa.git / blobdiff