radeonsi: use r600_common_context less pt1

[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.h

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h
index 4f3aa1fe3cebf1af404f32619694cdd6aaf0fc61..0f4b8598b50f36e021860ca393e9d2a33cbdcc70 100644 (file)
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -110,6 +110,7 @@ enum {
        DBG_NO_DCC_FB,
        DBG_NO_DCC_MSAA,
        DBG_DCC_MSAA,
+       DBG_NO_FMASK,
 
        /* Tests: */
        DBG_TEST_DMA,
@@ -363,16 +364,10 @@ struct r600_memory_object {
 /* This encapsulates a state or an operation which can emitted into the GPU
  * command stream. */
 struct r600_atom {
-       void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
+       void (*emit)(struct si_context *ctx, struct r600_atom *state);
        unsigned short          id;
 };
 
-struct r600_ring {
-       struct radeon_winsys_cs         *cs;
-       void (*flush)(void *ctx, unsigned flags,
-                     struct pipe_fence_handle **fence);
-};
-
 /* Saved CS data for debugging features. */
 struct radeon_saved_cs {
        uint32_t                        *ib;
@@ -390,8 +385,8 @@ struct r600_common_context {
        struct radeon_winsys_ctx        *ctx;
        enum radeon_family              family;
        enum chip_class                 chip_class;
-       struct r600_ring                gfx;
-       struct r600_ring                dma;
+       struct radeon_winsys_cs         *gfx_cs;
+       struct radeon_winsys_cs         *dma_cs;
        struct pipe_fence_handle        *last_gfx_fence;
        struct pipe_fence_handle        *last_sdma_fence;
        struct r600_resource            *eop_bug_scratch;
@@ -484,44 +479,6 @@ struct r600_common_context {
 
        void (*dma_clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
                                 uint64_t offset, uint64_t size, unsigned value);
-
-       void (*blit_decompress_depth)(struct pipe_context *ctx,
-                                     struct r600_texture *texture,
-                                     struct r600_texture *staging,
-                                     unsigned first_level, unsigned last_level,
-                                     unsigned first_layer, unsigned last_layer,
-                                     unsigned first_sample, unsigned last_sample);
-
-       void (*decompress_dcc)(struct pipe_context *ctx,
-                              struct r600_texture *rtex);
-
-       /* Reallocate the buffer and update all resource bindings where
-        * the buffer is bound, including all resource descriptors. */
-       void (*invalidate_buffer)(struct pipe_context *ctx, struct pipe_resource *buf);
-
-       /* Update all resource bindings where the buffer is bound, including
-        * all resource descriptors. This is invalidate_buffer without
-        * the invalidation. */
-       void (*rebind_buffer)(struct pipe_context *ctx, struct pipe_resource *buf,
-                             uint64_t old_gpu_address);
-
-       /* Enable or disable occlusion queries. */
-       void (*set_occlusion_query_state)(struct pipe_context *ctx,
-                                         bool old_enable,
-                                         bool old_perfect_enable);
-
-       void (*save_qbo_state)(struct pipe_context *ctx, struct r600_qbo_state *st);
-
-       /* This ensures there is enough space in the command stream. */
-       void (*need_gfx_cs_space)(struct pipe_context *ctx, unsigned num_dw,
-                                 bool include_draw_vbo);
-
-       void (*set_atom_dirty)(struct r600_common_context *ctx,
-                              struct r600_atom *atom, bool dirty);
-
-       void (*check_vm_faults)(struct r600_common_context *ctx,
-                               struct radeon_saved_cs *saved,
-                               enum ring_type ring);
 };
 
 /* r600_buffer_common.c */
@@ -548,25 +505,10 @@ void si_init_screen_buffer_functions(struct si_screen *sscreen);
 void si_init_buffer_functions(struct si_context *sctx);
 
 /* r600_common_pipe.c */
-void si_gfx_write_event_eop(struct r600_common_context *ctx,
-                           unsigned event, unsigned event_flags,
-                           unsigned data_sel,
-                           struct r600_resource *buf, uint64_t va,
-                           uint32_t new_fence, unsigned query_type);
-unsigned si_gfx_write_fence_dwords(struct si_screen *screen);
-void si_gfx_wait_fence(struct r600_common_context *ctx,
-                      uint64_t va, uint32_t ref, uint32_t mask);
 bool si_common_context_init(struct r600_common_context *rctx,
                            struct si_screen *sscreen,
                            unsigned context_flags);
 void si_common_context_cleanup(struct r600_common_context *rctx);
-void si_screen_clear_buffer(struct si_screen *sscreen, struct pipe_resource *dst,
-                           uint64_t offset, uint64_t size, unsigned value);
-void si_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
-                      struct r600_resource *dst, struct r600_resource *src);
-void si_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
-               struct radeon_saved_cs *saved, bool get_buffer_list);
-void si_clear_saved_cs(struct radeon_saved_cs *saved);
 bool si_check_device_reset(struct r600_common_context *rctx);
 
 /* r600_gpu_load.c */
@@ -599,6 +541,10 @@ void si_texture_get_fmask_info(struct si_screen *sscreen,
 void si_texture_get_cmask_info(struct si_screen *sscreen,
                               struct r600_texture *rtex,
                               struct r600_cmask_info *out);
+void si_eliminate_fast_color_clear(struct r600_common_context *rctx,
+                                  struct r600_texture *rtex);
+void si_texture_discard_cmask(struct si_screen *sscreen,
+                             struct r600_texture *rtex);
 bool si_init_flushed_depth_texture(struct pipe_context *ctx,
                                   struct pipe_resource *texture,
                                   struct r600_texture **staging);