gallium/radeon: don't use PREDICATION_OP_CLEAR

[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.h

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h
index 2df93e54559c435a86955658c458edc05b647988..139c377cd6e58862becc95cff83b4209fa8e4ce5 100644 (file)
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -99,6 +99,8 @@
 #define DBG_INFO               (1llu << 40)
 #define DBG_NO_WC              (1llu << 41)
 #define DBG_CHECK_VM           (1llu << 42)
+#define DBG_NO_DCC             (1llu << 43)
+#define DBG_NO_DCC_CLEAR       (1llu << 44)
 
 #define R600_MAP_BUFFER_ALIGNMENT 64
 
@@ -205,6 +207,7 @@ struct r600_texture {
        unsigned                        pitch_override;
        bool                            is_depth;
        unsigned                        dirty_level_mask; /* each bit says if that mipmap is compressed */
+       unsigned                        stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
        struct r600_texture             *flushed_depth_texture;
        boolean                         is_flushing_texture;
        struct radeon_surf              surface;
@@ -213,6 +216,7 @@ struct r600_texture {
        struct r600_fmask_info          fmask;
        struct r600_cmask_info          cmask;
        struct r600_resource            *cmask_buffer;
+       struct r600_resource            *dcc_buffer;
        unsigned                        cb_color_info; /* fast clear enable bit */
        unsigned                        color_clear_value[2];
 
@@ -242,6 +246,7 @@ struct r600_surface {
        unsigned cb_color_dim;          /* EG only */
        unsigned cb_color_pitch;        /* EG and later */
        unsigned cb_color_slice;        /* EG and later */
+       unsigned cb_dcc_base;           /* VI and later */
        unsigned cb_color_attrib;       /* EG and later */
        unsigned cb_dcc_control;        /* VI and later */
        unsigned cb_color_fmask;        /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
@@ -360,16 +365,10 @@ struct r600_streamout {
 
 struct r600_ring {
        struct radeon_winsys_cs         *cs;
-       bool                            flushing;
        void (*flush)(void *ctx, unsigned flags,
                      struct pipe_fence_handle **fence);
 };
 
-struct r600_rings {
-       struct r600_ring                gfx;
-       struct r600_ring                dma;
-};
-
 struct r600_common_context {
        struct pipe_context b; /* base class */
 
@@ -378,7 +377,9 @@ struct r600_common_context {
        struct radeon_winsys_ctx        *ctx;
        enum radeon_family              family;
        enum chip_class                 chip_class;
-       struct r600_rings               rings;
+       struct r600_ring                gfx;
+       struct r600_ring                dma;
+       struct pipe_fence_handle        *last_sdma_fence;
        unsigned                        initial_gfx_cs_size;
        unsigned                        gpu_reset_counter;
 
@@ -419,7 +420,8 @@ struct r600_common_context {
        struct pipe_query               *current_render_cond;
        unsigned                        current_render_cond_mode;
        boolean                         current_render_cond_cond;
-       boolean                         predicate_drawing;
+       bool                            predicate_drawing;
+       bool                            render_cond_force_off; /* for u_blitter */
        /* For context flushing. */
        struct pipe_query               *saved_render_cond;
        boolean                         saved_render_cond_cond;
@@ -488,6 +490,11 @@ bool r600_init_resource(struct r600_common_screen *rscreen,
 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
                                         const struct pipe_resource *templ,
                                         unsigned alignment);
+struct pipe_resource * r600_aligned_buffer_create(struct pipe_screen *screen,
+                                                 unsigned bind,
+                                                 unsigned usage,
+                                                 unsigned size,
+                                                 unsigned alignment);
 struct pipe_resource *
 r600_buffer_from_user_memory(struct pipe_screen *screen,
                             const struct pipe_resource *templ,
@@ -623,6 +630,18 @@ static inline unsigned r600_wavefront_size(enum radeon_family family)
        }
 }
 
+static inline enum radeon_bo_priority
+r600_get_sampler_view_priority(struct r600_resource *res)
+{
+       if (res->b.b.target == PIPE_BUFFER)
+               return RADEON_PRIO_SAMPLER_BUFFER;
+
+       if (res->b.b.nr_samples > 1)
+               return RADEON_PRIO_SAMPLER_TEXTURE_MSAA;
+
+       return RADEON_PRIO_SAMPLER_TEXTURE;
+}
+
 #define COMPUTE_DBG(rscreen, fmt, args...) \
        do { \
                if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \