gallium/radeon: don't use PREDICATION_OP_CLEAR
[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.h
index 72f4715975efb1bbfcc9b4baab05bd25d5f4833e..139c377cd6e58862becc95cff83b4209fa8e4ce5 100644 (file)
@@ -59,6 +59,8 @@
 #define R600_QUERY_CURRENT_GPU_SCLK    (PIPE_QUERY_DRIVER_SPECIFIC + 9)
 #define R600_QUERY_CURRENT_GPU_MCLK    (PIPE_QUERY_DRIVER_SPECIFIC + 10)
 #define R600_QUERY_GPU_LOAD            (PIPE_QUERY_DRIVER_SPECIFIC + 11)
+#define R600_QUERY_NUM_COMPILATIONS    (PIPE_QUERY_DRIVER_SPECIFIC + 12)
+#define R600_QUERY_NUM_SHADERS_CREATED (PIPE_QUERY_DRIVER_SPECIFIC + 13)
 
 #define R600_CONTEXT_STREAMOUT_FLUSH           (1u << 0)
 #define R600_CONTEXT_PRIVATE_FLAG              (1u << 1)
@@ -83,6 +85,7 @@
 #define DBG_TES                        (1 << 11)
 #define DBG_NO_IR              (1 << 12)
 #define DBG_NO_TGSI            (1 << 13)
+#define DBG_NO_ASM             (1 << 14)
 /* Bits 21-31 are reserved for the r600g driver. */
 /* features */
 #define DBG_NO_ASYNC_DMA       (1llu << 32)
 #define DBG_FORCE_DMA          (1llu << 38)
 #define DBG_PRECOMPILE         (1llu << 39)
 #define DBG_INFO               (1llu << 40)
+#define DBG_NO_WC              (1llu << 41)
+#define DBG_CHECK_VM           (1llu << 42)
+#define DBG_NO_DCC             (1llu << 43)
+#define DBG_NO_DCC_CLEAR       (1llu << 44)
 
 #define R600_MAP_BUFFER_ALIGNMENT 64
 
@@ -200,6 +207,7 @@ struct r600_texture {
        unsigned                        pitch_override;
        bool                            is_depth;
        unsigned                        dirty_level_mask; /* each bit says if that mipmap is compressed */
+       unsigned                        stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
        struct r600_texture             *flushed_depth_texture;
        boolean                         is_flushing_texture;
        struct radeon_surf              surface;
@@ -208,6 +216,7 @@ struct r600_texture {
        struct r600_fmask_info          fmask;
        struct r600_cmask_info          cmask;
        struct r600_resource            *cmask_buffer;
+       struct r600_resource            *dcc_buffer;
        unsigned                        cb_color_info; /* fast clear enable bit */
        unsigned                        color_clear_value[2];
 
@@ -237,7 +246,9 @@ struct r600_surface {
        unsigned cb_color_dim;          /* EG only */
        unsigned cb_color_pitch;        /* EG and later */
        unsigned cb_color_slice;        /* EG and later */
+       unsigned cb_dcc_base;           /* VI and later */
        unsigned cb_color_attrib;       /* EG and later */
+       unsigned cb_dcc_control;        /* VI and later */
        unsigned cb_color_fmask;        /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
        unsigned cb_color_fmask_slice;  /* EG and later */
        unsigned cb_color_cmask;        /* CB_COLORn_TILE (r600 only) */
@@ -287,12 +298,23 @@ struct r600_common_screen {
        uint32_t                        *trace_ptr;
        unsigned                        cs_count;
 
+       /* This must be in the screen, because UE4 uses one context for
+        * compilation and another one for rendering.
+        */
+       unsigned                        num_compilations;
+       /* Along with ST_DEBUG=precompile, this should show if applications
+        * are loading shaders on demand. This is a monotonic counter.
+        */
+       unsigned                        num_shaders_created;
+
        /* GPU load thread. */
        pipe_mutex                      gpu_load_mutex;
        pipe_thread                     gpu_load_thread;
        unsigned                        gpu_load_counter_busy;
        unsigned                        gpu_load_counter_idle;
        volatile unsigned               gpu_load_stop_thread; /* bool */
+
+       char                            renderer_string[64];
 };
 
 /* This encapsulates a state or an operation which can emitted into the GPU
@@ -300,7 +322,7 @@ struct r600_common_screen {
 struct r600_atom {
        void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
        unsigned                num_dw;
-       bool                    dirty;
+       unsigned short          id;
 };
 
 struct r600_so_target {
@@ -343,24 +365,21 @@ struct r600_streamout {
 
 struct r600_ring {
        struct radeon_winsys_cs         *cs;
-       bool                            flushing;
        void (*flush)(void *ctx, unsigned flags,
                      struct pipe_fence_handle **fence);
 };
 
-struct r600_rings {
-       struct r600_ring                gfx;
-       struct r600_ring                dma;
-};
-
 struct r600_common_context {
        struct pipe_context b; /* base class */
 
        struct r600_common_screen       *screen;
        struct radeon_winsys            *ws;
+       struct radeon_winsys_ctx        *ctx;
        enum radeon_family              family;
        enum chip_class                 chip_class;
-       struct r600_rings               rings;
+       struct r600_ring                gfx;
+       struct r600_ring                dma;
+       struct pipe_fence_handle        *last_sdma_fence;
        unsigned                        initial_gfx_cs_size;
        unsigned                        gpu_reset_counter;
 
@@ -383,11 +402,14 @@ struct r600_common_context {
        int                             num_occlusion_queries;
        /* Keep track of non-timer queries, because they should be suspended
         * during context flushing.
-        * The timer queries (TIME_ELAPSED) shouldn't be suspended. */
+        * The timer queries (TIME_ELAPSED) shouldn't be suspended for blits,
+        * but they should be suspended between IBs. */
        struct list_head                active_nontimer_queries;
+       struct list_head                active_timer_queries;
        unsigned                        num_cs_dw_nontimer_queries_suspend;
+       unsigned                        num_cs_dw_timer_queries_suspend;
        /* If queries have been suspended. */
-       bool                            nontimer_queries_suspended;
+       bool                            queries_suspended_for_flush;
        /* Additional hardware info. */
        unsigned                        backend_mask;
        unsigned                        max_db; /* for OQ */
@@ -398,7 +420,8 @@ struct r600_common_context {
        struct pipe_query               *current_render_cond;
        unsigned                        current_render_cond_mode;
        boolean                         current_render_cond_cond;
-       boolean                         predicate_drawing;
+       bool                            predicate_drawing;
+       bool                            render_cond_force_off; /* for u_blitter */
        /* For context flushing. */
        struct pipe_query               *saved_render_cond;
        boolean                         saved_render_cond_cond;
@@ -448,6 +471,9 @@ struct r600_common_context {
        /* This ensures there is enough space in the command stream. */
        void (*need_gfx_cs_space)(struct pipe_context *ctx, unsigned num_dw,
                                  bool include_draw_vbo);
+
+       void (*set_atom_dirty)(struct r600_common_context *ctx,
+                              struct r600_atom *atom, bool dirty);
 };
 
 /* r600_buffer.c */
@@ -464,6 +490,11 @@ bool r600_init_resource(struct r600_common_screen *rscreen,
 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
                                         const struct pipe_resource *templ,
                                         unsigned alignment);
+struct pipe_resource * r600_aligned_buffer_create(struct pipe_screen *screen,
+                                                 unsigned bind,
+                                                 unsigned usage,
+                                                 unsigned size,
+                                                 unsigned alignment);
 struct pipe_resource *
 r600_buffer_from_user_memory(struct pipe_screen *screen,
                             const struct pipe_resource *templ,
@@ -502,6 +533,8 @@ unsigned r600_gpu_load_end(struct r600_common_screen *rscreen, uint64_t begin);
 void r600_query_init(struct r600_common_context *rctx);
 void r600_suspend_nontimer_queries(struct r600_common_context *ctx);
 void r600_resume_nontimer_queries(struct r600_common_context *ctx);
+void r600_suspend_timer_queries(struct r600_common_context *ctx);
+void r600_resume_timer_queries(struct r600_common_context *ctx);
 void r600_query_init_backend_mask(struct r600_common_context *ctx);
 
 /* r600_streamout.c */
@@ -536,7 +569,7 @@ unsigned r600_translate_colorswap(enum pipe_format format);
 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
                                   struct pipe_framebuffer_state *fb,
                                   struct r600_atom *fb_state,
-                                  unsigned *buffers,
+                                  unsigned *buffers, unsigned *dirty_cbufs,
                                   const union pipe_color_union *color);
 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen);
 void r600_init_context_texture_functions(struct r600_common_context *rctx);
@@ -597,6 +630,18 @@ static inline unsigned r600_wavefront_size(enum radeon_family family)
        }
 }
 
+static inline enum radeon_bo_priority
+r600_get_sampler_view_priority(struct r600_resource *res)
+{
+       if (res->b.b.target == PIPE_BUFFER)
+               return RADEON_PRIO_SAMPLER_BUFFER;
+
+       if (res->b.b.nr_samples > 1)
+               return RADEON_PRIO_SAMPLER_TEXTURE_MSAA;
+
+       return RADEON_PRIO_SAMPLER_TEXTURE;
+}
+
 #define COMPUTE_DBG(rscreen, fmt, args...) \
        do { \
                if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \