#define DBG_INFO (1llu << 40)
#define DBG_NO_WC (1llu << 41)
#define DBG_CHECK_VM (1llu << 42)
+#define DBG_NO_DCC (1llu << 43)
+#define DBG_NO_DCC_CLEAR (1llu << 44)
#define R600_MAP_BUFFER_ALIGNMENT 64
struct r600_ring {
struct radeon_winsys_cs *cs;
- bool flushing;
void (*flush)(void *ctx, unsigned flags,
struct pipe_fence_handle **fence);
};
-struct r600_rings {
- struct r600_ring gfx;
- struct r600_ring dma;
-};
-
struct r600_common_context {
struct pipe_context b; /* base class */
struct radeon_winsys_ctx *ctx;
enum radeon_family family;
enum chip_class chip_class;
- struct r600_rings rings;
+ struct r600_ring gfx;
+ struct r600_ring dma;
+ struct pipe_fence_handle *last_sdma_fence;
unsigned initial_gfx_cs_size;
unsigned gpu_reset_counter;
struct pipe_query *current_render_cond;
unsigned current_render_cond_mode;
boolean current_render_cond_cond;
- boolean predicate_drawing;
+ bool predicate_drawing;
+ bool render_cond_force_off; /* for u_blitter */
/* For context flushing. */
struct pipe_query *saved_render_cond;
boolean saved_render_cond_cond;