#ifndef R600_PIPE_COMMON_H
#define R600_PIPE_COMMON_H
+#include <stdio.h>
+
#include "../../winsys/radeon/drm/radeon_winsys.h"
+#include "util/u_double_list.h"
#include "util/u_range.h"
+#include "util/u_slab.h"
#include "util/u_suballoc.h"
#include "util/u_transfer.h"
#define R600_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
#define R600_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
+#define R600_QUERY_DRAW_CALLS (PIPE_QUERY_DRIVER_SPECIFIC + 0)
+#define R600_QUERY_REQUESTED_VRAM (PIPE_QUERY_DRIVER_SPECIFIC + 1)
+#define R600_QUERY_REQUESTED_GTT (PIPE_QUERY_DRIVER_SPECIFIC + 2)
+#define R600_QUERY_BUFFER_WAIT_TIME (PIPE_QUERY_DRIVER_SPECIFIC + 3)
+
/* read caches */
#define R600_CONTEXT_INV_VERTEX_CACHE (1 << 0)
#define R600_CONTEXT_INV_TEX_CACHE (1 << 1)
#define R600_CONTEXT_PS_PARTIAL_FLUSH (1 << 16)
#define R600_CONTEXT_WAIT_3D_IDLE (1 << 17)
#define R600_CONTEXT_WAIT_CP_DMA_IDLE (1 << 18)
+#define R600_CONTEXT_VGT_FLUSH (1 << 19)
/* Debug flags. */
/* logging */
#define DBG_PS (1 << 11)
#define DBG_CS (1 << 12)
/* features */
-#define DBG_NO_HYPERZ (1 << 13)
+#define DBG_HYPERZ (1 << 13)
#define DBG_NO_DISCARD_RANGE (1 << 14)
/* The maximum allowed bit is 15. */
+#define R600_MAP_BUFFER_ALIGNMENT 64
+
struct r600_common_context;
struct r600_resource {
/* Colorbuffer compression and fast clear. */
struct r600_fmask_info fmask;
struct r600_cmask_info cmask;
-
- struct r600_resource *htile;
- float depth_clear; /* use htile only for first level */
-
struct r600_resource *cmask_buffer;
unsigned color_clear_value[2];
+ /* Depth buffer compression and fast clear. */
+ struct r600_resource *htile_buffer;
+ float depth_clear_value;
+
bool non_disp_tiling; /* R600-Cayman only */
unsigned mipmap_shift;
};
* It must be locked prior to using and flushed before unlocking. */
struct pipe_context *aux_context;
pipe_mutex aux_context_lock;
+
+ struct r600_resource *trace_bo;
+ uint32_t *trace_ptr;
+ unsigned cs_count;
};
/* This encapsulates a state or an operation which can emitted into the GPU
struct r600_common_context {
struct pipe_context b; /* base class */
+ struct r600_common_screen *screen;
struct radeon_winsys *ws;
enum radeon_family family;
enum chip_class chip_class;
struct r600_rings rings;
+ struct u_upload_mgr *uploader;
struct u_suballocator *allocator_so_filled_size;
+ struct util_slab_mempool pool_transfers;
/* Current unaccounted memory usage. */
uint64_t vram;
/* Additional context states. */
unsigned flags; /* flush flags */
+ /* Queries. */
+ /* The list of active queries. Only one query of each type can be active. */
+ int num_occlusion_queries;
+ int num_pipelinestat_queries;
+ /* Keep track of non-timer queries, because they should be suspended
+ * during context flushing.
+ * The timer queries (TIME_ELAPSED) shouldn't be suspended. */
+ struct list_head active_nontimer_queries;
+ unsigned num_cs_dw_nontimer_queries_suspend;
+ /* If queries have been suspended. */
+ bool nontimer_queries_suspended;
+ /* Additional hardware info. */
+ unsigned backend_mask;
+ unsigned max_db; /* for OQ */
+ /* Misc stats. */
+ unsigned num_draw_calls;
+
+ /* Render condition. */
+ struct pipe_query *current_render_cond;
+ unsigned current_render_cond_mode;
+ boolean current_render_cond_cond;
+ boolean predicate_drawing;
+
/* Copy one resource to another using async DMA.
* False is returned if the copy couldn't be done. */
boolean (*dma_copy)(struct pipe_context *ctx,
/* Reallocate the buffer and update all resource bindings where
* the buffer is bound, including all resource descriptors. */
void (*invalidate_buffer)(struct pipe_context *ctx, struct pipe_resource *buf);
+
+ /* Enable or disable occlusion queries. */
+ void (*set_occlusion_query_state)(struct pipe_context *ctx, bool enable);
+
+ /* This ensures there is enough space in the command stream. */
+ void (*need_gfx_cs_space)(struct pipe_context *ctx, unsigned num_dw,
+ bool include_draw_vbo);
};
/* r600_buffer.c */
bool r600_init_resource(struct r600_common_screen *rscreen,
struct r600_resource *res,
unsigned size, unsigned alignment,
- bool use_reusable_pool, unsigned usage);
+ bool use_reusable_pool);
+struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
+ const struct pipe_resource *templ,
+ unsigned alignment);
/* r600_common_pipe.c */
bool r600_common_screen_init(struct r600_common_screen *rscreen,
struct radeon_winsys *ws);
-void r600_common_screen_cleanup(struct r600_common_screen *rscreen);
+void r600_destroy_common_screen(struct r600_common_screen *rscreen);
bool r600_common_context_init(struct r600_common_context *rctx,
struct r600_common_screen *rscreen);
void r600_common_context_cleanup(struct r600_common_context *rctx);
const struct tgsi_token *tokens);
void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
unsigned offset, unsigned size, unsigned value);
+struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
+ const struct pipe_resource *templ);
+const char *r600_get_llvm_processor_name(enum radeon_family family);
+
+/* r600_query.c */
+void r600_query_init(struct r600_common_context *rctx);
+void r600_suspend_nontimer_queries(struct r600_common_context *ctx);
+void r600_resume_nontimer_queries(struct r600_common_context *ctx);
+void r600_query_init_backend_mask(struct r600_common_context *ctx);
/* r600_streamout.c */
void r600_streamout_buffers_dirty(struct r600_common_context *rctx);
struct r600_texture **staging);
struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
const struct pipe_resource *templ);
-struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
- const struct pipe_resource *base,
- struct winsys_handle *whandle);
+void r600_init_texture_functions(struct r600_common_screen *rscreen);
/* Inline helpers. */
projects / mesa.git / blobdiff