r600g,compute: provide local copy of functions from ac_binary.c

[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.h

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h
index 2feca0172faf37b89b8ba0915d28004467983e05..8ba5c369a66b5b818883f6b27fd0049ee2d22172 100644 (file)
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -34,8 +34,6 @@
 
 #include <stdio.h>
 
-#include "amd/common/ac_binary.h"
-
 #include "radeon/radeon_winsys.h"
 
 #include "util/disk_cache.h"
@@ -45,6 +43,7 @@
 #include "util/slab.h"
 #include "util/u_suballoc.h"
 #include "util/u_transfer.h"
+#include "util/u_threaded_context.h"
 
 #define ATI_VENDOR_ID 0x1002
 
@@ -107,6 +106,9 @@
 #define DBG_NO_CE              (1llu << 48)
 #define DBG_UNSAFE_MATH                (1llu << 49)
 #define DBG_NO_DCC_FB          (1llu << 50)
+#define DBG_TEST_VMFAULT_CP    (1llu << 51)
+#define DBG_TEST_VMFAULT_SDMA  (1llu << 52)
+#define DBG_TEST_VMFAULT_SHADER        (1llu << 53)
 
 #define R600_MAP_BUFFER_ALIGNMENT 64
 #define R600_MAX_VIEWPORTS        16
@@ -130,14 +132,11 @@ struct r600_perfcounters;
 struct tgsi_shader_info;
 struct r600_qbo_state;
 
-void radeon_shader_binary_init(struct ac_shader_binary *b);
-void radeon_shader_binary_clean(struct ac_shader_binary *b);
-
 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
  * at the moment.
  */
 struct r600_resource {
-       struct u_resource               b;
+       struct threaded_resource        b;
 
        /* Winsys objects. */
        struct pb_buffer                *buf;
@@ -176,12 +175,15 @@ struct r600_resource {
        bool                            TC_L2_dirty;
 
        /* Whether the resource has been exported via resource_get_handle. */
-       bool                            is_shared;
        unsigned                        external_usage; /* PIPE_HANDLE_USAGE_* */
+
+       /* Whether this resource is referenced by bindless handles. */
+       bool                            texture_handle_allocated;
+       bool                            image_handle_allocated;
 };
 
 struct r600_transfer {
-       struct pipe_transfer            transfer;
+       struct threaded_transfer        b;
        struct r600_resource            *staging;
        unsigned                        offset;
 };
@@ -229,7 +231,7 @@ struct r600_texture {
        unsigned                        last_msaa_resolve_target_micro_mode;
 
        /* Depth buffer compression and fast clear. */
-       struct r600_resource            *htile_buffer;
+       uint64_t                        htile_offset;
        bool                            tc_compatible_htile;
        bool                            depth_cleared; /* if it was cleared at least once */
        float                           depth_clear_value;
@@ -287,6 +289,7 @@ struct r600_surface {
        bool export_16bpc;
        bool color_is_int8;
        bool color_is_int10;
+       bool dcc_incompatible;
 
        /* Color registers. */
        unsigned cb_color_info;
@@ -482,7 +485,7 @@ struct r600_streamout {
 
        /* External state which comes from the vertex shader,
         * it must be set explicitly when binding a shader. */
-       unsigned                        *stride_in_dw;
+       uint16_t                        *stride_in_dw;
        unsigned                        enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
 
        /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
@@ -549,8 +552,10 @@ struct r600_common_context {
        unsigned                        last_dirty_tex_counter;
        unsigned                        last_compressed_colortex_counter;
 
+       struct threaded_context         *tc;
        struct u_suballocator           *allocator_zeroed_memory;
        struct slab_child_pool          pool_transfers;
+       struct slab_child_pool          pool_transfers_unsync; /* for threaded_context */
 
        /* Current unaccounted memory usage. */
        uint64_t                        vram;
@@ -576,6 +581,7 @@ struct r600_common_context {
        unsigned                        num_cs_dw_queries_suspend;
        /* Misc stats. */
        unsigned                        num_draw_calls;
+       unsigned                        num_prim_restart_calls;
        unsigned                        num_spill_draw_calls;
        unsigned                        num_compute_calls;
        unsigned                        num_spill_compute_calls;
@@ -660,6 +666,12 @@ struct r600_common_context {
         * the buffer is bound, including all resource descriptors. */
        void (*invalidate_buffer)(struct pipe_context *ctx, struct pipe_resource *buf);
 
+       /* Update all resource bindings where the buffer is bound, including
+        * all resource descriptors. This is invalidate_buffer without
+        * the invalidation. */
+       void (*rebind_buffer)(struct pipe_context *ctx, struct pipe_resource *buf,
+                             uint64_t old_gpu_address);
+
        /* Enable or disable occlusion queries. */
        void (*set_occlusion_query_state)(struct pipe_context *ctx, bool enable);
 
@@ -677,7 +689,7 @@ struct r600_common_context {
                                enum ring_type ring);
 };
 
-/* r600_buffer.c */
+/* r600_buffer_common.c */
 bool r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
                                     struct pb_buffer *buf,
                                     enum radeon_bo_usage usage);
@@ -708,6 +720,9 @@ r600_buffer_from_user_memory(struct pipe_screen *screen,
 void
 r600_invalidate_resource(struct pipe_context *ctx,
                         struct pipe_resource *resource);
+void r600_replace_buffer_storage(struct pipe_context *ctx,
+                                struct pipe_resource *dst,
+                                struct pipe_resource *src);
 
 /* r600_common_pipe.c */
 void r600_gfx_write_event_eop(struct r600_common_context *ctx,
@@ -801,6 +816,9 @@ struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
                                        const struct pipe_resource *templ);
 bool vi_dcc_formats_compatible(enum pipe_format format1,
                               enum pipe_format format2);
+bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex,
+                                    unsigned level,
+                                    enum pipe_format view_format);
 void vi_disable_dcc_if_incompatible_format(struct r600_common_context *rctx,
                                           struct pipe_resource *tex,
                                           unsigned level,
@@ -823,7 +841,7 @@ void vi_dcc_clear_level(struct r600_common_context *rctx,
 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
                                   struct pipe_framebuffer_state *fb,
                                   struct r600_atom *fb_state,
-                                  unsigned *buffers, unsigned *dirty_cbufs,
+                                  unsigned *buffers, ubyte *dirty_cbufs,
                                   const union pipe_color_union *color);
 bool r600_texture_disable_dcc(struct r600_common_context *rctx,
                              struct r600_texture *rtex);