#include "radeon/radeon_winsys.h"
+#include "util/disk_cache.h"
#include "util/u_blitter.h"
#include "util/list.h"
#include "util/u_range.h"
#include "util/slab.h"
#include "util/u_suballoc.h"
#include "util/u_transfer.h"
+#include "util/u_threaded_context.h"
#define ATI_VENDOR_ID 0x1002
#define R600_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
#define R600_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
#define R600_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
+#define R600_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
#define R600_CONTEXT_STREAMOUT_FLUSH (1u << 0)
/* Pipeline & streamout query controls. */
#define DBG_NO_CE (1llu << 48)
#define DBG_UNSAFE_MATH (1llu << 49)
#define DBG_NO_DCC_FB (1llu << 50)
+#define DBG_TEST_VMFAULT_CP (1llu << 51)
+#define DBG_TEST_VMFAULT_SDMA (1llu << 52)
+#define DBG_TEST_VMFAULT_SHADER (1llu << 53)
#define R600_MAP_BUFFER_ALIGNMENT 64
#define R600_MAX_VIEWPORTS 16
struct tgsi_shader_info;
struct r600_qbo_state;
-struct radeon_shader_reloc {
- char name[32];
- uint64_t offset;
-};
-
-struct radeon_shader_binary {
- /** Shader code */
- unsigned char *code;
- unsigned code_size;
-
- /** Config/Context register state that accompanies this shader.
- * This is a stream of dword pairs. First dword contains the
- * register address, the second dword contains the value.*/
- unsigned char *config;
- unsigned config_size;
-
- /** The number of bytes of config information for each global symbol.
- */
- unsigned config_size_per_symbol;
-
- /** Constant data accessed by the shader. This will be uploaded
- * into a constant buffer. */
- unsigned char *rodata;
- unsigned rodata_size;
-
- /** List of symbol offsets for the shader */
- uint64_t *global_symbol_offsets;
- unsigned global_symbol_count;
-
- struct radeon_shader_reloc *relocs;
- unsigned reloc_count;
-
- /** Disassembled shader in a string. */
- char *disasm_string;
- char *llvm_ir_string;
-};
-
-void radeon_shader_binary_init(struct radeon_shader_binary *b);
-void radeon_shader_binary_clean(struct radeon_shader_binary *b);
-
/* Only 32-bit buffer allocations are supported, gallium doesn't support more
* at the moment.
*/
struct r600_resource {
- struct u_resource b;
+ struct threaded_resource b;
/* Winsys objects. */
struct pb_buffer *buf;
bool TC_L2_dirty;
/* Whether the resource has been exported via resource_get_handle. */
- bool is_shared;
unsigned external_usage; /* PIPE_HANDLE_USAGE_* */
+
+ /* Whether this resource is referenced by bindless handles. */
+ bool texture_handle_allocated;
+ bool image_handle_allocated;
};
struct r600_transfer {
- struct pipe_transfer transfer;
+ struct threaded_transfer b;
struct r600_resource *staging;
unsigned offset;
};
uint64_t size;
unsigned alignment;
unsigned slice_tile_max;
- unsigned base_address_reg;
+ uint64_t base_address_reg;
};
struct r600_texture {
unsigned last_msaa_resolve_target_micro_mode;
/* Depth buffer compression and fast clear. */
- struct r600_resource *htile_buffer;
+ uint64_t htile_offset;
bool tc_compatible_htile;
bool depth_cleared; /* if it was cleared at least once */
float depth_clear_value;
struct r600_surface {
struct pipe_surface base;
+ /* These can vary with block-compressed textures. */
+ unsigned width0;
+ unsigned height0;
+
bool color_initialized;
bool depth_initialized;
bool alphatest_bypass;
bool export_16bpc;
bool color_is_int8;
+ bool color_is_int10;
+ bool dcc_incompatible;
/* Color registers. */
unsigned cb_color_info;
unsigned cb_color_pitch; /* EG and later */
unsigned cb_color_slice; /* EG and later */
unsigned cb_color_attrib; /* EG and later */
+ unsigned cb_color_attrib2; /* GFX9 and later */
unsigned cb_dcc_control; /* VI and later */
unsigned cb_color_fmask; /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
unsigned cb_color_fmask_slice; /* EG and later */
struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */
/* DB registers. */
+ uint64_t db_depth_base; /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
+ uint64_t db_stencil_base; /* EG and later */
+ uint64_t db_htile_data_base;
unsigned db_depth_info; /* R600 only, then SI and later */
unsigned db_z_info; /* EG and later */
- unsigned db_depth_base; /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
+ unsigned db_z_info2; /* GFX9+ */
unsigned db_depth_view;
unsigned db_depth_size;
unsigned db_depth_slice; /* EG and later */
- unsigned db_stencil_base; /* EG and later */
unsigned db_stencil_info; /* EG and later */
+ unsigned db_stencil_info2; /* GFX9+ */
unsigned db_prefetch_limit; /* R600 only */
unsigned db_htile_surface;
- unsigned db_htile_data_base;
unsigned db_preload_control; /* EG and later */
};
-struct r600_grbm_counter {
+struct r600_mmio_counter {
unsigned busy;
unsigned idle;
};
-union r600_grbm_counters {
+union r600_mmio_counters {
struct {
- struct r600_grbm_counter spi;
- struct r600_grbm_counter gui;
- struct r600_grbm_counter ta;
- struct r600_grbm_counter gds;
- struct r600_grbm_counter vgt;
- struct r600_grbm_counter ia;
- struct r600_grbm_counter sx;
- struct r600_grbm_counter wd;
- struct r600_grbm_counter bci;
- struct r600_grbm_counter sc;
- struct r600_grbm_counter pa;
- struct r600_grbm_counter db;
- struct r600_grbm_counter cp;
- struct r600_grbm_counter cb;
+ /* For global GPU load including SDMA. */
+ struct r600_mmio_counter gpu;
+
+ /* GRBM_STATUS */
+ struct r600_mmio_counter spi;
+ struct r600_mmio_counter gui;
+ struct r600_mmio_counter ta;
+ struct r600_mmio_counter gds;
+ struct r600_mmio_counter vgt;
+ struct r600_mmio_counter ia;
+ struct r600_mmio_counter sx;
+ struct r600_mmio_counter wd;
+ struct r600_mmio_counter bci;
+ struct r600_mmio_counter sc;
+ struct r600_mmio_counter pa;
+ struct r600_mmio_counter db;
+ struct r600_mmio_counter cp;
+ struct r600_mmio_counter cb;
+
+ /* SRBM_STATUS2 */
+ struct r600_mmio_counter sdma;
+
+ /* CP_STAT */
+ struct r600_mmio_counter pfp;
+ struct r600_mmio_counter meq;
+ struct r600_mmio_counter me;
+ struct r600_mmio_counter surf_sync;
+ struct r600_mmio_counter dma;
+ struct r600_mmio_counter scratch_ram;
+ struct r600_mmio_counter ce;
} named;
unsigned array[0];
};
uint64_t debug_flags;
bool has_cp_dma;
bool has_streamout;
+ bool has_rbplus; /* if RB+ registers exist */
+ bool rbplus_allowed; /* if RB+ is allowed */
+
+ struct disk_cache *disk_shader_cache;
struct slab_parent_pool pool_transfers;
/* Auxiliary context. Mainly used to initialize resources.
* It must be locked prior to using and flushed before unlocking. */
struct pipe_context *aux_context;
- pipe_mutex aux_context_lock;
+ mtx_t aux_context_lock;
/* This must be in the screen, because UE4 uses one context for
* compilation and another one for rendering.
unsigned num_shader_cache_hits;
/* GPU load thread. */
- pipe_mutex gpu_load_mutex;
- pipe_thread gpu_load_thread;
- union r600_grbm_counters grbm_counters;
+ mtx_t gpu_load_mutex;
+ thrd_t gpu_load_thread;
+ union r600_mmio_counters mmio_counters;
volatile unsigned gpu_load_stop_thread; /* bool */
char renderer_string[100];
/* Performance counters. */
struct r600_perfcounters *perfcounters;
- /* If pipe_screen wants to re-emit the framebuffer state of all
- * contexts, it should atomically increment this. Each context will
- * compare this with its own last known value of the counter before
- * drawing and re-emit the framebuffer state accordingly.
+ /* If pipe_screen wants to recompute and re-emit the framebuffer,
+ * sampler, and image states of all contexts, it should atomically
+ * increment this.
+ *
+ * Each context will compare this with its own last known value of
+ * the counter before drawing and re-emit the states accordingly.
*/
- unsigned dirty_fb_counter;
+ unsigned dirty_tex_counter;
/* Atomically increment this counter when an existing texture's
* metadata is enabled or disabled in a way that requires changing
*/
unsigned compressed_colortex_counter;
- /* Atomically increment this counter when an existing texture's
- * backing buffer or tile mode parameters have changed that requires
- * recomputation of shader descriptors.
- */
- unsigned dirty_tex_descriptor_counter;
-
struct {
/* Context flags to set so that all writes from earlier jobs
* in the CP are seen by L2 clients.
/* External state which comes from the vertex shader,
* it must be set explicitly when binding a shader. */
- unsigned *stride_in_dw;
+ uint16_t *stride_in_dw;
unsigned enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
/* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
unsigned num_gfx_cs_flushes;
unsigned initial_gfx_cs_size;
unsigned gpu_reset_counter;
- unsigned last_dirty_fb_counter;
+ unsigned last_dirty_tex_counter;
unsigned last_compressed_colortex_counter;
- unsigned last_dirty_tex_descriptor_counter;
- struct u_upload_mgr *uploader;
+ struct threaded_context *tc;
struct u_suballocator *allocator_zeroed_memory;
struct slab_child_pool pool_transfers;
+ struct slab_child_pool pool_transfers_unsync; /* for threaded_context */
/* Current unaccounted memory usage. */
uint64_t vram;
int num_perfect_occlusion_queries;
struct list_head active_queries;
unsigned num_cs_dw_queries_suspend;
- /* Additional hardware info. */
- unsigned max_db; /* for OQ */
/* Misc stats. */
unsigned num_draw_calls;
+ unsigned num_prim_restart_calls;
unsigned num_spill_draw_calls;
unsigned num_compute_calls;
unsigned num_spill_compute_calls;
* the buffer is bound, including all resource descriptors. */
void (*invalidate_buffer)(struct pipe_context *ctx, struct pipe_resource *buf);
+ /* Update all resource bindings where the buffer is bound, including
+ * all resource descriptors. This is invalidate_buffer without
+ * the invalidation. */
+ void (*rebind_buffer)(struct pipe_context *ctx, struct pipe_resource *buf,
+ uint64_t old_gpu_address);
+
/* Enable or disable occlusion queries. */
void (*set_occlusion_query_state)(struct pipe_context *ctx, bool enable);
enum ring_type ring);
};
-/* r600_buffer.c */
+/* r600_buffer_common.c */
bool r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
struct pb_buffer *buf,
enum radeon_bo_usage usage);
const struct pipe_resource *templ,
unsigned alignment);
struct pipe_resource * r600_aligned_buffer_create(struct pipe_screen *screen,
- unsigned bind,
+ unsigned flags,
unsigned usage,
unsigned size,
unsigned alignment);
void
r600_invalidate_resource(struct pipe_context *ctx,
struct pipe_resource *resource);
+void r600_replace_buffer_storage(struct pipe_context *ctx,
+ struct pipe_resource *dst,
+ struct pipe_resource *src);
/* r600_common_pipe.c */
void r600_gfx_write_event_eop(struct r600_common_context *ctx,
bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
struct pipe_resource *texture,
struct r600_texture **staging);
-void r600_print_texture_info(struct r600_texture *rtex, FILE *f);
+void r600_print_texture_info(struct r600_common_screen *rscreen,
+ struct r600_texture *rtex, FILE *f);
struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
const struct pipe_resource *templ);
bool vi_dcc_formats_compatible(enum pipe_format format1,
enum pipe_format format2);
-void vi_dcc_disable_if_incompatible_format(struct r600_common_context *rctx,
+bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex,
+ unsigned level,
+ enum pipe_format view_format);
+void vi_disable_dcc_if_incompatible_format(struct r600_common_context *rctx,
struct pipe_resource *tex,
unsigned level,
enum pipe_format view_format);
struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
struct pipe_resource *texture,
const struct pipe_surface *templ,
+ unsigned width0, unsigned height0,
unsigned width, unsigned height);
unsigned r600_translate_colorswap(enum pipe_format format, bool do_endian_swap);
void vi_separate_dcc_start_query(struct pipe_context *ctx,
void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
struct pipe_framebuffer_state *fb,
struct r600_atom *fb_state,
- unsigned *buffers, unsigned *dirty_cbufs,
+ unsigned *buffers, ubyte *dirty_cbufs,
const union pipe_color_union *color);
bool r600_texture_disable_dcc(struct r600_common_context *rctx,
struct r600_texture *rtex);
(!stencil_sampler && tex->can_sample_z);
}
+static inline bool
+vi_dcc_enabled(struct r600_texture *tex, unsigned level)
+{
+ return tex->dcc_offset && level < tex->surface.num_dcc_levels;
+}
+
#define COMPUTE_DBG(rscreen, fmt, args...) \
do { \
if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
projects / mesa.git / blobdiff