struct r600_texture {
struct r600_resource resource;
+ struct radeon_surf surface;
uint64_t size;
- unsigned num_level0_transfers;
- enum pipe_format db_render_format;
- bool is_depth;
- bool db_compatible;
- bool can_sample_z;
- bool can_sample_s;
- unsigned dirty_level_mask; /* each bit says if that mipmap is compressed */
- unsigned stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
struct r600_texture *flushed_depth_texture;
- struct radeon_surf surface;
/* Colorbuffer compression and fast clear. */
struct r600_fmask_info fmask;
unsigned cb_color_info; /* fast clear enable bit */
unsigned color_clear_value[2];
unsigned last_msaa_resolve_target_micro_mode;
+ unsigned num_level0_transfers;
/* Depth buffer compression and fast clear. */
uint64_t htile_offset;
- bool tc_compatible_htile;
- bool depth_cleared; /* if it was cleared at least once */
float depth_clear_value;
- bool stencil_cleared; /* if it was cleared at least once */
+ uint16_t dirty_level_mask; /* each bit says if that mipmap is compressed */
+ uint16_t stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
+ enum pipe_format db_render_format:16;
uint8_t stencil_clear_value;
- bool upgraded_depth; /* upgraded from unorm to Z32_FLOAT */
+ bool tc_compatible_htile:1;
+ bool depth_cleared:1; /* if it was cleared at least once */
+ bool stencil_cleared:1; /* if it was cleared at least once */
+ bool upgraded_depth:1; /* upgraded from unorm to Z32_FLOAT */
+ bool is_depth:1;
+ bool db_compatible:1;
+ bool can_sample_z:1;
+ bool can_sample_s:1;
+ /* We need to track DCC dirtiness, because st/dri usually calls
+ * flush_resource twice per frame (not a bug) and we don't wanna
+ * decompress DCC twice. Also, the dirty tracking must be done even
+ * if DCC isn't used, because it's required by the DCC usage analysis
+ * for a possible future enablement.
+ */
+ bool separate_dcc_dirty:1;
+ /* Statistics gathering for the DCC enablement heuristic. */
+ bool dcc_gather_statistics:1;
+ /* Counter that should be non-zero if the texture is bound to a
+ * framebuffer.
+ */
+ unsigned framebuffers_bound;
/* Whether the texture is a displayable back buffer and needs DCC
* decompression, which is expensive. Therefore, it's enabled only
* if statistics suggest that it will pay off and it's allocated
struct r600_resource *dcc_separate_buffer;
/* When DCC is temporarily disabled, the separate buffer is here. */
struct r600_resource *last_dcc_separate_buffer;
- /* We need to track DCC dirtiness, because st/dri usually calls
- * flush_resource twice per frame (not a bug) and we don't wanna
- * decompress DCC twice. Also, the dirty tracking must be done even
- * if DCC isn't used, because it's required by the DCC usage analysis
- * for a possible future enablement.
- */
- bool separate_dcc_dirty;
- /* Statistics gathering for the DCC enablement heuristic. */
- bool dcc_gather_statistics;
/* Estimate of how much this color buffer is written to in units of
* full-screen draws: ps_invocations / (width * height)
* Shader kills, late Z, and blending with trivial discards make it
unsigned ps_draw_ratio;
/* The number of clears since the last DCC usage analysis. */
unsigned num_slow_clears;
-
- /* Counter that should be non-zero if the texture is bound to a
- * framebuffer. Implemented in radeonsi only.
- */
- uint32_t framebuffers_bound;
};
struct r600_surface {
struct pipe_surface base;
/* These can vary with block-compressed textures. */
- unsigned width0;
- unsigned height0;
+ uint16_t width0;
+ uint16_t height0;
- bool color_initialized;
- bool depth_initialized;
+ bool color_initialized:1;
+ bool depth_initialized:1;
/* Misc. color flags. */
- bool color_is_int8;
- bool color_is_int10;
- bool dcc_incompatible;
+ bool color_is_int8:1;
+ bool color_is_int10:1;
+ bool dcc_incompatible:1;
/* Color registers. */
unsigned cb_color_info;
unsigned cb_color_attrib;
unsigned cb_color_attrib2; /* GFX9 and later */
unsigned cb_dcc_control; /* VI and later */
- unsigned spi_shader_col_format; /* no blending, no alpha-to-coverage. */
- unsigned spi_shader_col_format_alpha; /* alpha-to-coverage */
- unsigned spi_shader_col_format_blend; /* blending without alpha. */
- unsigned spi_shader_col_format_blend_alpha; /* blending with alpha. */
+ unsigned spi_shader_col_format:8; /* no blending, no alpha-to-coverage. */
+ unsigned spi_shader_col_format_alpha:8; /* alpha-to-coverage */
+ unsigned spi_shader_col_format_blend:8; /* blending without alpha. */
+ unsigned spi_shader_col_format_blend_alpha:8; /* blending with alpha. */
/* DB registers. */
uint64_t db_depth_base; /* DB_Z_READ/WRITE_BASE */
enum chip_class chip_class;
struct radeon_info info;
uint64_t debug_flags;
- bool has_cp_dma;
- bool has_streamout;
bool has_rbplus; /* if RB+ registers exist */
bool rbplus_allowed; /* if RB+ is allowed */
projects / mesa.git / blobdiff