/*
* Copyright 2013 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
#define R600_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
#define R600_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
#define R600_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
+#define R600_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
+#define R600_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
/* Debug flags. */
enum {
/* Shader compiler options (with no effect on the shader cache): */
DBG_CHECK_IR,
- DBG_PRECOMPILE,
DBG_NIR,
DBG_MONOLITHIC_SHADERS,
DBG_NO_OPT_VARIANT,
DBG_NO_DCC_FB,
DBG_NO_DCC_MSAA,
DBG_DCC_MSAA,
+ DBG_NO_FMASK,
/* Tests: */
DBG_TEST_DMA,
/* This encapsulates a state or an operation which can emitted into the GPU
* command stream. */
struct r600_atom {
- void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
+ void (*emit)(struct si_context *ctx, struct r600_atom *state);
unsigned short id;
};
-struct r600_ring {
- struct radeon_winsys_cs *cs;
- void (*flush)(void *ctx, unsigned flags,
- struct pipe_fence_handle **fence);
-};
-
/* Saved CS data for debugging features. */
struct radeon_saved_cs {
uint32_t *ib;
struct radeon_winsys_ctx *ctx;
enum radeon_family family;
enum chip_class chip_class;
- struct r600_ring gfx;
- struct r600_ring dma;
+ struct radeon_winsys_cs *gfx_cs;
+ struct radeon_winsys_cs *dma_cs;
struct pipe_fence_handle *last_gfx_fence;
struct pipe_fence_handle *last_sdma_fence;
struct r600_resource *eop_bug_scratch;
+ struct u_upload_mgr *cached_gtt_allocator;
unsigned num_gfx_cs_flushes;
unsigned initial_gfx_cs_size;
unsigned gpu_reset_counter;
void (*dma_clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
uint64_t offset, uint64_t size, unsigned value);
-
- void (*blit_decompress_depth)(struct pipe_context *ctx,
- struct r600_texture *texture,
- struct r600_texture *staging,
- unsigned first_level, unsigned last_level,
- unsigned first_layer, unsigned last_layer,
- unsigned first_sample, unsigned last_sample);
-
- void (*decompress_dcc)(struct pipe_context *ctx,
- struct r600_texture *rtex);
-
- /* Reallocate the buffer and update all resource bindings where
- * the buffer is bound, including all resource descriptors. */
- void (*invalidate_buffer)(struct pipe_context *ctx, struct pipe_resource *buf);
-
- /* Update all resource bindings where the buffer is bound, including
- * all resource descriptors. This is invalidate_buffer without
- * the invalidation. */
- void (*rebind_buffer)(struct pipe_context *ctx, struct pipe_resource *buf,
- uint64_t old_gpu_address);
-
- /* Enable or disable occlusion queries. */
- void (*set_occlusion_query_state)(struct pipe_context *ctx,
- bool old_enable,
- bool old_perfect_enable);
-
- void (*save_qbo_state)(struct pipe_context *ctx, struct r600_qbo_state *st);
-
- /* This ensures there is enough space in the command stream. */
- void (*need_gfx_cs_space)(struct pipe_context *ctx, unsigned num_dw,
- bool include_draw_vbo);
-
- void (*set_atom_dirty)(struct r600_common_context *ctx,
- struct r600_atom *atom, bool dirty);
-
- void (*check_vm_faults)(struct r600_common_context *ctx,
- struct radeon_saved_cs *saved,
- enum ring_type ring);
};
/* r600_buffer_common.c */
-bool si_rings_is_buffer_referenced(struct r600_common_context *ctx,
+bool si_rings_is_buffer_referenced(struct si_context *sctx,
struct pb_buffer *buf,
enum radeon_bo_usage usage);
-void *si_buffer_map_sync_with_rings(struct r600_common_context *ctx,
+void *si_buffer_map_sync_with_rings(struct si_context *sctx,
struct r600_resource *resource,
unsigned usage);
void si_init_resource_fields(struct si_screen *sscreen,
void si_init_buffer_functions(struct si_context *sctx);
/* r600_common_pipe.c */
-void si_gfx_write_event_eop(struct r600_common_context *ctx,
- unsigned event, unsigned event_flags,
- unsigned data_sel,
- struct r600_resource *buf, uint64_t va,
- uint32_t new_fence, unsigned query_type);
-unsigned si_gfx_write_fence_dwords(struct si_screen *screen);
-void si_gfx_wait_fence(struct r600_common_context *ctx,
- uint64_t va, uint32_t ref, uint32_t mask);
bool si_common_context_init(struct r600_common_context *rctx,
struct si_screen *sscreen,
unsigned context_flags);
void si_common_context_cleanup(struct r600_common_context *rctx);
-void si_screen_clear_buffer(struct si_screen *sscreen, struct pipe_resource *dst,
- uint64_t offset, uint64_t size, unsigned value);
-void si_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
- struct r600_resource *dst, struct r600_resource *src);
-void si_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
- struct radeon_saved_cs *saved, bool get_buffer_list);
-void si_clear_saved_cs(struct radeon_saved_cs *saved);
bool si_check_device_reset(struct r600_common_context *rctx);
/* r600_gpu_load.c */
/* r600_query.c */
void si_init_screen_query_functions(struct si_screen *sscreen);
-void si_init_query_functions(struct r600_common_context *rctx);
-void si_suspend_queries(struct r600_common_context *ctx);
-void si_resume_queries(struct r600_common_context *ctx);
+void si_init_query_functions(struct si_context *sctx);
+void si_suspend_queries(struct si_context *sctx);
+void si_resume_queries(struct si_context *sctx);
/* r600_texture.c */
-bool si_prepare_for_dma_blit(struct r600_common_context *rctx,
+bool si_prepare_for_dma_blit(struct si_context *sctx,
struct r600_texture *rdst,
unsigned dst_level, unsigned dstx,
unsigned dsty, unsigned dstz,
void si_texture_get_cmask_info(struct si_screen *sscreen,
struct r600_texture *rtex,
struct r600_cmask_info *out);
+void si_eliminate_fast_color_clear(struct si_context *sctx,
+ struct r600_texture *rtex);
+void si_texture_discard_cmask(struct si_screen *sscreen,
+ struct r600_texture *rtex);
bool si_init_flushed_depth_texture(struct pipe_context *ctx,
struct pipe_resource *texture,
struct r600_texture **staging);
bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex,
unsigned level,
enum pipe_format view_format);
-void vi_disable_dcc_if_incompatible_format(struct r600_common_context *rctx,
+void vi_disable_dcc_if_incompatible_format(struct si_context *sctx,
struct pipe_resource *tex,
unsigned level,
enum pipe_format view_format);
unsigned width0, unsigned height0,
unsigned width, unsigned height);
unsigned si_translate_colorswap(enum pipe_format format, bool do_endian_swap);
-void vi_separate_dcc_try_enable(struct r600_common_context *rctx,
+void vi_separate_dcc_try_enable(struct si_context *sctx,
struct r600_texture *tex);
void vi_separate_dcc_start_query(struct pipe_context *ctx,
struct r600_texture *tex);
struct r600_texture *tex);
void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
struct r600_texture *tex);
-bool si_texture_disable_dcc(struct r600_common_context *rctx,
+bool si_texture_disable_dcc(struct si_context *sctx,
struct r600_texture *rtex);
void si_init_screen_texture_functions(struct si_screen *sscreen);
-void si_init_context_texture_functions(struct r600_common_context *rctx);
+void si_init_context_texture_functions(struct si_context *sctx);
/* Inline helpers. */
projects / mesa.git / blobdiff