* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
- *
- * Authors: Marek Olšák <maraeo@gmail.com>
- *
*/
/**
#define R600_NOT_QUERY 0xffffffff
/* Debug flags. */
-#define DBG_VS (1 << PIPE_SHADER_VERTEX)
-#define DBG_PS (1 << PIPE_SHADER_FRAGMENT)
-#define DBG_GS (1 << PIPE_SHADER_GEOMETRY)
-#define DBG_TCS (1 << PIPE_SHADER_TESS_CTRL)
-#define DBG_TES (1 << PIPE_SHADER_TESS_EVAL)
-#define DBG_CS (1 << PIPE_SHADER_COMPUTE)
-#define DBG_ALL_SHADERS (DBG_FS - 1)
-#define DBG_FS (1 << 6) /* fetch shader */
-#define DBG_TEX (1 << 7)
-#define DBG_NIR (1 << 8)
-#define DBG_COMPUTE (1 << 9)
-/* gap */
-#define DBG_VM (1 << 11)
-#define DBG_NO_IR (1 << 12)
-#define DBG_NO_TGSI (1 << 13)
-#define DBG_NO_ASM (1 << 14)
-#define DBG_PREOPT_IR (1 << 15)
-#define DBG_CHECK_IR (1 << 16)
-#define DBG_NO_OPT_VARIANT (1 << 17)
-#define DBG_FS_CORRECT_DERIVS_AFTER_KILL (1 << 18)
-/* gaps */
-#define DBG_TEST_DMA (1 << 20)
-/* Bits 21-31 are reserved for the r600g driver. */
-/* features */
-#define DBG_NO_ASYNC_DMA (1ull << 32)
-#define DBG_NO_HYPERZ (1ull << 33)
-#define DBG_NO_DISCARD_RANGE (1ull << 34)
-#define DBG_NO_2D_TILING (1ull << 35)
-#define DBG_NO_TILING (1ull << 36)
-#define DBG_SWITCH_ON_EOP (1ull << 37)
-#define DBG_FORCE_DMA (1ull << 38)
-#define DBG_PRECOMPILE (1ull << 39)
-#define DBG_INFO (1ull << 40)
-#define DBG_NO_WC (1ull << 41)
-#define DBG_CHECK_VM (1ull << 42)
-#define DBG_NO_DCC (1ull << 43)
-#define DBG_NO_DCC_CLEAR (1ull << 44)
-#define DBG_NO_RB_PLUS (1ull << 45)
-#define DBG_SI_SCHED (1ull << 46)
-#define DBG_MONOLITHIC_SHADERS (1ull << 47)
-#define DBG_NO_OUT_OF_ORDER (1ull << 48)
-#define DBG_UNSAFE_MATH (1ull << 49)
-#define DBG_NO_DCC_FB (1ull << 50)
-#define DBG_TEST_VMFAULT_CP (1ull << 51)
-#define DBG_TEST_VMFAULT_SDMA (1ull << 52)
-#define DBG_TEST_VMFAULT_SHADER (1ull << 53)
-#define DBG_NO_DPBB (1ull << 54)
-#define DBG_NO_DFSM (1ull << 55)
+enum {
+ /* Shader logging options: */
+ DBG_VS = PIPE_SHADER_VERTEX,
+ DBG_PS = PIPE_SHADER_FRAGMENT,
+ DBG_GS = PIPE_SHADER_GEOMETRY,
+ DBG_TCS = PIPE_SHADER_TESS_CTRL,
+ DBG_TES = PIPE_SHADER_TESS_EVAL,
+ DBG_CS = PIPE_SHADER_COMPUTE,
+ DBG_NO_IR,
+ DBG_NO_TGSI,
+ DBG_NO_ASM,
+ DBG_PREOPT_IR,
+
+ /* Shader compiler options the shader cache should be aware of: */
+ DBG_FS_CORRECT_DERIVS_AFTER_KILL,
+ DBG_UNSAFE_MATH,
+ DBG_SI_SCHED,
+
+ /* Shader compiler options (with no effect on the shader cache): */
+ DBG_CHECK_IR,
+ DBG_PRECOMPILE,
+ DBG_NIR,
+ DBG_MONOLITHIC_SHADERS,
+ DBG_NO_OPT_VARIANT,
+
+ /* Information logging options: */
+ DBG_INFO,
+ DBG_TEX,
+ DBG_COMPUTE,
+ DBG_VM,
+
+ /* Driver options: */
+ DBG_FORCE_DMA,
+ DBG_NO_ASYNC_DMA,
+ DBG_NO_WC,
+ DBG_CHECK_VM,
+ DBG_RESERVE_VMID,
+
+ /* 3D engine options: */
+ DBG_SWITCH_ON_EOP,
+ DBG_NO_OUT_OF_ORDER,
+ DBG_NO_DPBB,
+ DBG_NO_DFSM,
+ DBG_DPBB,
+ DBG_DFSM,
+ DBG_NO_HYPERZ,
+ DBG_NO_RB_PLUS,
+ DBG_NO_2D_TILING,
+ DBG_NO_TILING,
+ DBG_NO_DCC,
+ DBG_NO_DCC_CLEAR,
+ DBG_NO_DCC_FB,
+
+ /* Tests: */
+ DBG_TEST_DMA,
+ DBG_TEST_VMFAULT_CP,
+ DBG_TEST_VMFAULT_SDMA,
+ DBG_TEST_VMFAULT_SHADER,
+};
+
+#define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
+#define DBG(name) (1ull << DBG_##name)
#define R600_MAP_BUFFER_ALIGNMENT 64
enum radeon_bo_domain domains;
enum radeon_bo_flag flags;
unsigned bind_history;
+ int max_forced_staging_uploads;
/* The buffer range which is initialized (with a write transfer,
* streamout, DMA, or as a random access target). The rest of
uint8_t stencil_clear_value;
bool upgraded_depth; /* upgraded from unorm to Z32_FLOAT */
- bool non_disp_tiling; /* R600-Cayman only */
-
/* Whether the texture is a displayable back buffer and needs DCC
* decompression, which is expensive. Therefore, it's enabled only
* if statistics suggest that it will pay off and it's allocated
bool depth_initialized;
/* Misc. color flags. */
- bool alphatest_bypass;
- bool export_16bpc;
bool color_is_int8;
bool color_is_int10;
bool dcc_incompatible;
/* Color registers. */
unsigned cb_color_info;
- unsigned cb_color_base;
unsigned cb_color_view;
- unsigned cb_color_size; /* R600 only */
- unsigned cb_color_dim; /* EG only */
- unsigned cb_color_pitch; /* EG and later */
- unsigned cb_color_slice; /* EG and later */
- unsigned cb_color_attrib; /* EG and later */
+ unsigned cb_color_attrib;
unsigned cb_color_attrib2; /* GFX9 and later */
unsigned cb_dcc_control; /* VI and later */
- unsigned cb_color_fmask; /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
- unsigned cb_color_fmask_slice; /* EG and later */
- unsigned cb_color_cmask; /* CB_COLORn_TILE (r600 only) */
- unsigned cb_color_mask; /* R600 only */
- unsigned spi_shader_col_format; /* SI+, no blending, no alpha-to-coverage. */
- unsigned spi_shader_col_format_alpha; /* SI+, alpha-to-coverage */
- unsigned spi_shader_col_format_blend; /* SI+, blending without alpha. */
- unsigned spi_shader_col_format_blend_alpha; /* SI+, blending with alpha. */
- struct r600_resource *cb_buffer_fmask; /* Used for FMASK relocations. R600 only */
- struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */
+ unsigned spi_shader_col_format; /* no blending, no alpha-to-coverage. */
+ unsigned spi_shader_col_format_alpha; /* alpha-to-coverage */
+ unsigned spi_shader_col_format_blend; /* blending without alpha. */
+ unsigned spi_shader_col_format_blend_alpha; /* blending with alpha. */
/* DB registers. */
- uint64_t db_depth_base; /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
- uint64_t db_stencil_base; /* EG and later */
+ uint64_t db_depth_base; /* DB_Z_READ/WRITE_BASE */
+ uint64_t db_stencil_base;
uint64_t db_htile_data_base;
- unsigned db_depth_info; /* R600 only, then SI and later */
- unsigned db_z_info; /* EG and later */
+ unsigned db_depth_info;
+ unsigned db_z_info;
unsigned db_z_info2; /* GFX9+ */
unsigned db_depth_view;
unsigned db_depth_size;
- unsigned db_depth_slice; /* EG and later */
- unsigned db_stencil_info; /* EG and later */
+ unsigned db_depth_slice;
+ unsigned db_stencil_info;
unsigned db_stencil_info2; /* GFX9+ */
- unsigned db_prefetch_limit; /* R600 only */
unsigned db_htile_surface;
- unsigned db_preload_control; /* EG and later */
};
struct r600_mmio_counter {
unsigned short id;
};
-struct r600_so_target {
- struct pipe_stream_output_target b;
-
- /* The buffer where BUFFER_FILLED_SIZE is stored. */
- struct r600_resource *buf_filled_size;
- unsigned buf_filled_size_offset;
- bool buf_filled_size_valid;
-
- unsigned stride_in_dw;
-};
-
-struct r600_streamout {
- struct r600_atom begin_atom;
- bool begin_emitted;
-
- unsigned enabled_mask;
- unsigned num_targets;
- struct r600_so_target *targets[PIPE_MAX_SO_BUFFERS];
-
- unsigned append_bitmask;
- bool suspended;
-
- /* External state which comes from the vertex shader,
- * it must be set explicitly when binding a shader. */
- uint16_t *stride_in_dw;
- unsigned enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
-
- /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
- unsigned hw_enabled_mask;
-
- /* The state of VGT_STRMOUT_(CONFIG|EN). */
- struct r600_atom enable_atom;
- bool streamout_enabled;
- bool prims_gen_query_enabled;
- int num_prims_gen_queries;
-};
-
struct r600_ring {
struct radeon_winsys_cs *cs;
void (*flush)(void *ctx, unsigned flags,
uint64_t vram;
uint64_t gtt;
- /* States. */
- struct r600_streamout streamout;
-
/* Additional context states. */
unsigned flags; /* flush flags */
bool render_cond_invert;
bool render_cond_force_off; /* for u_blitter */
- /* MSAA sample locations.
- * The first index is the sample index.
- * The second index is the coordinate: X, Y. */
- float sample_locations_1x[1][2];
- float sample_locations_2x[2][2];
- float sample_locations_4x[4][2];
- float sample_locations_8x[8][2];
- float sample_locations_16x[16][2];
-
/* Statistics gathering for the DCC enablement heuristic. It can't be
* in r600_texture because r600_texture can be shared by multiple
* contexts. This is for back buffers only. We shouldn't get too many
bool query_active;
} dcc_stats[5];
- struct pipe_debug_callback debug;
struct pipe_device_reset_callback device_reset_callback;
struct u_log_context *log;
uint64_t offset, uint64_t size, unsigned value);
struct pipe_resource *si_resource_create_common(struct pipe_screen *screen,
const struct pipe_resource *templ);
-const char *si_get_llvm_processor_name(enum radeon_family family);
void si_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
struct r600_resource *dst, struct r600_resource *src);
void si_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
void si_suspend_queries(struct r600_common_context *ctx);
void si_resume_queries(struct r600_common_context *ctx);
-/* r600_streamout.c */
-void si_streamout_buffers_dirty(struct r600_common_context *rctx);
-void si_common_set_streamout_targets(struct pipe_context *ctx,
- unsigned num_targets,
- struct pipe_stream_output_target **targets,
- const unsigned *offset);
-void si_emit_streamout_end(struct r600_common_context *rctx);
-void si_update_prims_generated_query_state(struct r600_common_context *rctx,
- unsigned type, int diff);
-void si_streamout_init(struct r600_common_context *rctx);
-
/* r600_test_dma.c */
void si_test_dma(struct r600_common_screen *rscreen);
void si_init_screen_texture_functions(struct r600_common_screen *rscreen);
void si_init_context_texture_functions(struct r600_common_context *rctx);
-/* cayman_msaa.c */
-void si_get_sample_position(struct pipe_context *ctx, unsigned sample_count,
- unsigned sample_index, float *out_value);
-void si_init_msaa(struct pipe_context *ctx);
-void si_common_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
-void si_common_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
- int ps_iter_samples, int overrast_samples,
- unsigned sc_mode_cntl_1);
-
/* Inline helpers. */
}
}
-static inline bool r600_get_strmout_en(struct r600_common_context *rctx)
-{
- return rctx->streamout.streamout_enabled ||
- rctx->streamout.prims_gen_query_enabled;
-}
-
#define SQ_TEX_XY_FILTER_POINT 0x00
#define SQ_TEX_XY_FILTER_BILINEAR 0x01
#define SQ_TEX_XY_FILTER_ANISO_POINT 0x02
#define COMPUTE_DBG(rscreen, fmt, args...) \
do { \
- if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
+ if ((rscreen->b.debug_flags & DBG(COMPUTE))) fprintf(stderr, fmt, ##args); \
} while (0);
#define R600_ERR(fmt, args...) \
fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
-/* For MSAA sample positions. */
-#define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
- (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) | \
- (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
- (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
- (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
-
static inline int S_FIXED(float value, unsigned frac_bits)
{
return value * (1 << frac_bits);
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