#include "os/os_time.h"
#include "tgsi/tgsi_text.h"
+/* TODO: remove this: */
+void si_update_prims_generated_query_state(struct r600_common_context *rctx,
+ unsigned type, int diff);
+
#define R600_MAX_STREAMS 4
struct r600_hw_query_params {
case R600_QUERY_GPU_SURF_SYNC_BUSY:
case R600_QUERY_GPU_CP_DMA_BUSY:
case R600_QUERY_GPU_SCRATCH_RAM_BUSY:
- case R600_QUERY_GPU_CE_BUSY:
- query->begin_result = r600_begin_counter(rctx->screen,
+ query->begin_result = si_begin_counter(rctx->screen,
query->b.type);
break;
case R600_QUERY_NUM_COMPILATIONS:
case R600_QUERY_GPU_SURF_SYNC_BUSY:
case R600_QUERY_GPU_CP_DMA_BUSY:
case R600_QUERY_GPU_SCRATCH_RAM_BUSY:
- case R600_QUERY_GPU_CE_BUSY:
- query->end_result = r600_end_counter(rctx->screen,
+ query->end_result = si_end_counter(rctx->screen,
query->b.type,
query->begin_result);
query->begin_result = 0;
return (struct pipe_query *)query;
}
-void r600_query_hw_destroy(struct r600_common_screen *rscreen,
- struct r600_query *rquery)
+void si_query_hw_destroy(struct r600_common_screen *rscreen,
+ struct r600_query *rquery)
{
struct r600_query_hw *query = (struct r600_query_hw *)rquery;
struct r600_query_buffer *prev = query->buffer.previous;
memset(results, 0, buffer->b.b.width0);
if (query->b.type == PIPE_QUERY_OCCLUSION_COUNTER ||
- query->b.type == PIPE_QUERY_OCCLUSION_PREDICATE) {
+ query->b.type == PIPE_QUERY_OCCLUSION_PREDICATE ||
+ query->b.type == PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE) {
unsigned max_rbs = rscreen->info.num_render_backends;
unsigned enabled_rb_mask = rscreen->info.enabled_rb_mask;
unsigned num_results;
unsigned offset);
static struct r600_query_ops query_hw_ops = {
- .destroy = r600_query_hw_destroy,
- .begin = r600_query_hw_begin,
- .end = r600_query_hw_end,
- .get_result = r600_query_hw_get_result,
+ .destroy = si_query_hw_destroy,
+ .begin = si_query_hw_begin,
+ .end = si_query_hw_end,
+ .get_result = si_query_hw_get_result,
.get_result_resource = r600_query_hw_get_result_resource,
};
.add_result = r600_query_hw_add_result,
};
-bool r600_query_hw_init(struct r600_common_screen *rscreen,
- struct r600_query_hw *query)
+bool si_query_hw_init(struct r600_common_screen *rscreen,
+ struct r600_query_hw *query)
{
query->buffer.buf = r600_new_query_buffer(rscreen, query);
if (!query->buffer.buf)
switch (query_type) {
case PIPE_QUERY_OCCLUSION_COUNTER:
case PIPE_QUERY_OCCLUSION_PREDICATE:
+ case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
query->result_size = 16 * rscreen->info.num_render_backends;
query->result_size += 16; /* for the fence + alignment */
query->num_cs_dw_begin = 6;
- query->num_cs_dw_end = 6 + r600_gfx_write_fence_dwords(rscreen);
+ query->num_cs_dw_end = 6 + si_gfx_write_fence_dwords(rscreen);
break;
case PIPE_QUERY_TIME_ELAPSED:
query->result_size = 24;
query->num_cs_dw_begin = 8;
- query->num_cs_dw_end = 8 + r600_gfx_write_fence_dwords(rscreen);
+ query->num_cs_dw_end = 8 + si_gfx_write_fence_dwords(rscreen);
break;
case PIPE_QUERY_TIMESTAMP:
query->result_size = 16;
- query->num_cs_dw_end = 8 + r600_gfx_write_fence_dwords(rscreen);
+ query->num_cs_dw_end = 8 + si_gfx_write_fence_dwords(rscreen);
query->flags = R600_QUERY_HW_FLAG_NO_START;
break;
case PIPE_QUERY_PRIMITIVES_EMITTED:
query->num_cs_dw_end = 6 * R600_MAX_STREAMS;
break;
case PIPE_QUERY_PIPELINE_STATISTICS:
- /* 11 values on EG, 8 on R600. */
- query->result_size = (rscreen->chip_class >= EVERGREEN ? 11 : 8) * 16;
+ /* 11 values on GCN. */
+ query->result_size = 11 * 16;
query->result_size += 8; /* for the fence + alignment */
query->num_cs_dw_begin = 6;
- query->num_cs_dw_end = 6 + r600_gfx_write_fence_dwords(rscreen);
+ query->num_cs_dw_end = 6 + si_gfx_write_fence_dwords(rscreen);
break;
default:
assert(0);
return NULL;
}
- if (!r600_query_hw_init(rscreen, query)) {
+ if (!si_query_hw_init(rscreen, query)) {
FREE(query);
return NULL;
}
unsigned type, int diff)
{
if (type == PIPE_QUERY_OCCLUSION_COUNTER ||
- type == PIPE_QUERY_OCCLUSION_PREDICATE) {
+ type == PIPE_QUERY_OCCLUSION_PREDICATE ||
+ type == PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE) {
bool old_enable = rctx->num_occlusion_queries != 0;
bool old_perfect_enable =
rctx->num_perfect_occlusion_queries != 0;
rctx->num_occlusion_queries += diff;
assert(rctx->num_occlusion_queries >= 0);
- if (type == PIPE_QUERY_OCCLUSION_COUNTER) {
+ if (type != PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE) {
rctx->num_perfect_occlusion_queries += diff;
assert(rctx->num_perfect_occlusion_queries >= 0);
}
perfect_enable = rctx->num_perfect_occlusion_queries != 0;
if (enable != old_enable || perfect_enable != old_perfect_enable) {
- rctx->set_occlusion_query_state(&rctx->b, enable);
+ rctx->set_occlusion_query_state(&rctx->b, old_enable,
+ old_perfect_enable);
}
}
}
switch (query->b.type) {
case PIPE_QUERY_OCCLUSION_COUNTER:
case PIPE_QUERY_OCCLUSION_PREDICATE:
+ case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
radeon_emit(cs, va);
emit_sample_streamout(cs, va + 32 * stream, stream);
break;
case PIPE_QUERY_TIME_ELAPSED:
- if (ctx->chip_class >= SI) {
- /* Write the timestamp from the CP not waiting for
- * outstanding draws (top-of-pipe).
- */
- radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
- radeon_emit(cs, COPY_DATA_COUNT_SEL |
- COPY_DATA_SRC_SEL(COPY_DATA_TIMESTAMP) |
- COPY_DATA_DST_SEL(COPY_DATA_MEM_ASYNC));
- radeon_emit(cs, 0);
- radeon_emit(cs, 0);
- radeon_emit(cs, va);
- radeon_emit(cs, va >> 32);
- } else {
- /* Write the timestamp after the last draw is done.
- * (bottom-of-pipe)
- */
- r600_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS,
- 0, 3, NULL, va, 0, 0);
- }
+ /* Write the timestamp from the CP not waiting for
+ * outstanding draws (top-of-pipe).
+ */
+ radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
+ radeon_emit(cs, COPY_DATA_COUNT_SEL |
+ COPY_DATA_SRC_SEL(COPY_DATA_TIMESTAMP) |
+ COPY_DATA_DST_SEL(COPY_DATA_MEM_ASYNC));
+ radeon_emit(cs, 0);
+ radeon_emit(cs, 0);
+ radeon_emit(cs, va);
+ radeon_emit(cs, va >> 32);
break;
case PIPE_QUERY_PIPELINE_STATISTICS:
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
return; // previous buffer allocation failure
r600_update_occlusion_query_state(ctx, query->b.type, 1);
- r600_update_prims_generated_query_state(ctx, query->b.type, 1);
+ si_update_prims_generated_query_state(ctx, query->b.type, 1);
ctx->need_gfx_cs_space(&ctx->b, query->num_cs_dw_begin + query->num_cs_dw_end,
true);
switch (query->b.type) {
case PIPE_QUERY_OCCLUSION_COUNTER:
case PIPE_QUERY_OCCLUSION_PREDICATE:
+ case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
va += 8;
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
va += 8;
/* fall through */
case PIPE_QUERY_TIMESTAMP:
- r600_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS,
- 0, 3, NULL, va, 0, 0);
+ si_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS,
+ 0, EOP_DATA_SEL_TIMESTAMP, NULL, va,
+ 0, query->b.type);
fence_va = va + 8;
break;
case PIPE_QUERY_PIPELINE_STATISTICS: {
RADEON_PRIO_QUERY);
if (fence_va)
- r600_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0, 1,
- query->buffer.buf, fence_va, 0, 0x80000000);
+ si_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0,
+ EOP_DATA_SEL_VALUE_32BIT,
+ query->buffer.buf, fence_va, 0x80000000,
+ query->b.type);
}
static void r600_query_hw_emit_stop(struct r600_common_context *ctx,
ctx->num_cs_dw_queries_suspend -= query->num_cs_dw_end;
r600_update_occlusion_query_state(ctx, query->b.type, -1);
- r600_update_prims_generated_query_state(ctx, query->b.type, -1);
+ si_update_prims_generated_query_state(ctx, query->b.type, -1);
}
static void emit_set_predicate(struct r600_common_context *ctx,
switch (query->b.type) {
case PIPE_QUERY_OCCLUSION_COUNTER:
case PIPE_QUERY_OCCLUSION_PREDICATE:
+ case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
op = PRED_OP(PREDICATION_OP_ZPASS);
break;
case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
return rquery->ops->begin(rctx, rquery);
}
-void r600_query_hw_reset_buffers(struct r600_common_context *rctx,
- struct r600_query_hw *query)
+void si_query_hw_reset_buffers(struct r600_common_context *rctx,
+ struct r600_query_hw *query)
{
struct r600_query_buffer *prev = query->buffer.previous;
query->buffer.previous = NULL;
/* Obtain a new buffer if the current one can't be mapped without a stall. */
- if (r600_rings_is_buffer_referenced(rctx, query->buffer.buf->buf, RADEON_USAGE_READWRITE) ||
+ if (si_rings_is_buffer_referenced(rctx, query->buffer.buf->buf, RADEON_USAGE_READWRITE) ||
!rctx->ws->buffer_wait(query->buffer.buf->buf, 0, RADEON_USAGE_READWRITE)) {
r600_resource_reference(&query->buffer.buf, NULL);
query->buffer.buf = r600_new_query_buffer(rctx->screen, query);
}
}
-bool r600_query_hw_begin(struct r600_common_context *rctx,
- struct r600_query *rquery)
+bool si_query_hw_begin(struct r600_common_context *rctx,
+ struct r600_query *rquery)
{
struct r600_query_hw *query = (struct r600_query_hw *)rquery;
}
if (!(query->flags & R600_QUERY_HW_FLAG_BEGIN_RESUMES))
- r600_query_hw_reset_buffers(rctx, query);
+ si_query_hw_reset_buffers(rctx, query);
r600_resource_reference(&query->workaround_buf, NULL);
return rquery->ops->end(rctx, rquery);
}
-bool r600_query_hw_end(struct r600_common_context *rctx,
- struct r600_query *rquery)
+bool si_query_hw_end(struct r600_common_context *rctx,
+ struct r600_query *rquery)
{
struct r600_query_hw *query = (struct r600_query_hw *)rquery;
if (query->flags & R600_QUERY_HW_FLAG_NO_START)
- r600_query_hw_reset_buffers(rctx, query);
+ si_query_hw_reset_buffers(rctx, query);
r600_query_hw_emit_stop(rctx, query);
switch (rquery->b.type) {
case PIPE_QUERY_OCCLUSION_COUNTER:
case PIPE_QUERY_OCCLUSION_PREDICATE:
+ case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
params->start_offset = 0;
params->end_offset = 8;
params->fence_offset = max_rbs * 16;
}
break;
}
- case PIPE_QUERY_OCCLUSION_PREDICATE: {
+ case PIPE_QUERY_OCCLUSION_PREDICATE:
+ case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE: {
for (unsigned i = 0; i < max_rbs; ++i) {
unsigned results_base = i * 16;
result->b = result->b ||
}
break;
case PIPE_QUERY_PIPELINE_STATISTICS:
- if (rscreen->chip_class >= EVERGREEN) {
- result->pipeline_statistics.ps_invocations +=
- r600_query_read_result(buffer, 0, 22, false);
- result->pipeline_statistics.c_primitives +=
- r600_query_read_result(buffer, 2, 24, false);
- result->pipeline_statistics.c_invocations +=
- r600_query_read_result(buffer, 4, 26, false);
- result->pipeline_statistics.vs_invocations +=
- r600_query_read_result(buffer, 6, 28, false);
- result->pipeline_statistics.gs_invocations +=
- r600_query_read_result(buffer, 8, 30, false);
- result->pipeline_statistics.gs_primitives +=
- r600_query_read_result(buffer, 10, 32, false);
- result->pipeline_statistics.ia_primitives +=
- r600_query_read_result(buffer, 12, 34, false);
- result->pipeline_statistics.ia_vertices +=
- r600_query_read_result(buffer, 14, 36, false);
- result->pipeline_statistics.hs_invocations +=
- r600_query_read_result(buffer, 16, 38, false);
- result->pipeline_statistics.ds_invocations +=
- r600_query_read_result(buffer, 18, 40, false);
- result->pipeline_statistics.cs_invocations +=
- r600_query_read_result(buffer, 20, 42, false);
- } else {
- result->pipeline_statistics.ps_invocations +=
- r600_query_read_result(buffer, 0, 16, false);
- result->pipeline_statistics.c_primitives +=
- r600_query_read_result(buffer, 2, 18, false);
- result->pipeline_statistics.c_invocations +=
- r600_query_read_result(buffer, 4, 20, false);
- result->pipeline_statistics.vs_invocations +=
- r600_query_read_result(buffer, 6, 22, false);
- result->pipeline_statistics.gs_invocations +=
- r600_query_read_result(buffer, 8, 24, false);
- result->pipeline_statistics.gs_primitives +=
- r600_query_read_result(buffer, 10, 26, false);
- result->pipeline_statistics.ia_primitives +=
- r600_query_read_result(buffer, 12, 28, false);
- result->pipeline_statistics.ia_vertices +=
- r600_query_read_result(buffer, 14, 30, false);
- }
+ result->pipeline_statistics.ps_invocations +=
+ r600_query_read_result(buffer, 0, 22, false);
+ result->pipeline_statistics.c_primitives +=
+ r600_query_read_result(buffer, 2, 24, false);
+ result->pipeline_statistics.c_invocations +=
+ r600_query_read_result(buffer, 4, 26, false);
+ result->pipeline_statistics.vs_invocations +=
+ r600_query_read_result(buffer, 6, 28, false);
+ result->pipeline_statistics.gs_invocations +=
+ r600_query_read_result(buffer, 8, 30, false);
+ result->pipeline_statistics.gs_primitives +=
+ r600_query_read_result(buffer, 10, 32, false);
+ result->pipeline_statistics.ia_primitives +=
+ r600_query_read_result(buffer, 12, 34, false);
+ result->pipeline_statistics.ia_vertices +=
+ r600_query_read_result(buffer, 14, 36, false);
+ result->pipeline_statistics.hs_invocations +=
+ r600_query_read_result(buffer, 16, 38, false);
+ result->pipeline_statistics.ds_invocations +=
+ r600_query_read_result(buffer, 18, 40, false);
+ result->pipeline_statistics.cs_invocations +=
+ r600_query_read_result(buffer, 20, 42, false);
#if 0 /* for testing */
printf("Pipeline stats: IA verts=%llu, IA prims=%llu, VS=%llu, HS=%llu, "
"DS=%llu, GS=%llu, GS prims=%llu, Clipper=%llu, "
util_query_clear_result(result, query->b.type);
}
-bool r600_query_hw_get_result(struct r600_common_context *rctx,
- struct r600_query *rquery,
- bool wait, union pipe_query_result *result)
+bool si_query_hw_get_result(struct r600_common_context *rctx,
+ struct r600_query *rquery,
+ bool wait, union pipe_query_result *result)
{
struct r600_common_screen *rscreen = rctx->screen;
struct r600_query_hw *query = (struct r600_query_hw *)rquery;
if (rquery->b.flushed)
map = rctx->ws->buffer_map(qbuf->buf->buf, NULL, usage);
else
- map = r600_buffer_map_sync_with_rings(rctx, qbuf->buf, usage);
+ map = si_buffer_map_sync_with_rings(rctx, qbuf->buf, usage);
if (!map)
return false;
"DCL BUFFER[0]\n"
"DCL BUFFER[1]\n"
"DCL BUFFER[2]\n"
- "DCL CONST[0..1]\n"
+ "DCL CONST[0][0..1]\n"
"DCL TEMP[0..5]\n"
"IMM[0] UINT32 {0, 31, 2147483647, 4294967295}\n"
"IMM[1] UINT32 {1, 2, 4, 8}\n"
"IMM[3] UINT32 {1000000, 0, %u, 0}\n" /* for timestamp conversion */
"IMM[4] UINT32 {256, 0, 0, 0}\n"
- "AND TEMP[5], CONST[0].wwww, IMM[2].xxxx\n"
+ "AND TEMP[5], CONST[0][0].wwww, IMM[2].xxxx\n"
"UIF TEMP[5]\n"
/* Check result availability. */
- "LOAD TEMP[1].x, BUFFER[0], CONST[1].xxxx\n"
+ "LOAD TEMP[1].x, BUFFER[0], CONST[0][1].xxxx\n"
"ISHR TEMP[0].z, TEMP[1].xxxx, IMM[0].yyyy\n"
"MOV TEMP[1], TEMP[0].zzzz\n"
"NOT TEMP[0].z, TEMP[0].zzzz\n"
"ELSE\n"
/* Load previously accumulated result if requested. */
"MOV TEMP[0], IMM[0].xxxx\n"
- "AND TEMP[4], CONST[0].wwww, IMM[1].xxxx\n"
+ "AND TEMP[4], CONST[0][0].wwww, IMM[1].xxxx\n"
"UIF TEMP[4]\n"
"LOAD TEMP[0].xyz, BUFFER[1], IMM[0].xxxx\n"
"ENDIF\n"
"ENDIF\n"
/* Break if result_index >= result_count. */
- "USGE TEMP[5], TEMP[1].xxxx, CONST[0].zzzz\n"
+ "USGE TEMP[5], TEMP[1].xxxx, CONST[0][0].zzzz\n"
"UIF TEMP[5]\n"
"BRK\n"
"ENDIF\n"
/* Load fence and check result availability */
- "UMAD TEMP[5].x, TEMP[1].xxxx, CONST[0].yyyy, CONST[1].xxxx\n"
+ "UMAD TEMP[5].x, TEMP[1].xxxx, CONST[0][0].yyyy, CONST[0][1].xxxx\n"
"LOAD TEMP[5].x, BUFFER[0], TEMP[5].xxxx\n"
"ISHR TEMP[0].z, TEMP[5].xxxx, IMM[0].yyyy\n"
"NOT TEMP[0].z, TEMP[0].zzzz\n"
"MOV TEMP[1].y, IMM[0].xxxx\n"
"BGNLOOP\n"
/* Load start and end. */
- "UMUL TEMP[5].x, TEMP[1].xxxx, CONST[0].yyyy\n"
- "UMAD TEMP[5].x, TEMP[1].yyyy, CONST[1].yyyy, TEMP[5].xxxx\n"
+ "UMUL TEMP[5].x, TEMP[1].xxxx, CONST[0][0].yyyy\n"
+ "UMAD TEMP[5].x, TEMP[1].yyyy, CONST[0][1].yyyy, TEMP[5].xxxx\n"
"LOAD TEMP[2].xy, BUFFER[0], TEMP[5].xxxx\n"
- "UADD TEMP[5].y, TEMP[5].xxxx, CONST[0].xxxx\n"
+ "UADD TEMP[5].y, TEMP[5].xxxx, CONST[0][0].xxxx\n"
"LOAD TEMP[3].xy, BUFFER[0], TEMP[5].yyyy\n"
"U64ADD TEMP[4].xy, TEMP[3], -TEMP[2]\n"
- "AND TEMP[5].z, CONST[0].wwww, IMM[4].xxxx\n"
+ "AND TEMP[5].z, CONST[0][0].wwww, IMM[4].xxxx\n"
"UIF TEMP[5].zzzz\n"
/* Load second start/end half-pair and
* take the difference
/* Increment pair index */
"UADD TEMP[1].y, TEMP[1].yyyy, IMM[1].xxxx\n"
- "USGE TEMP[5], TEMP[1].yyyy, CONST[1].zzzz\n"
+ "USGE TEMP[5], TEMP[1].yyyy, CONST[0][1].zzzz\n"
"UIF TEMP[5]\n"
"BRK\n"
"ENDIF\n"
"ENDLOOP\n"
"ENDIF\n"
- "AND TEMP[4], CONST[0].wwww, IMM[1].yyyy\n"
+ "AND TEMP[4], CONST[0][0].wwww, IMM[1].yyyy\n"
"UIF TEMP[4]\n"
/* Store accumulated data for chaining. */
"STORE BUFFER[2].xyz, IMM[0].xxxx, TEMP[0]\n"
"ELSE\n"
- "AND TEMP[4], CONST[0].wwww, IMM[1].zzzz\n"
+ "AND TEMP[4], CONST[0][0].wwww, IMM[1].zzzz\n"
"UIF TEMP[4]\n"
/* Store result availability. */
"NOT TEMP[0].z, TEMP[0]\n"
"AND TEMP[0].z, TEMP[0].zzzz, IMM[1].xxxx\n"
"STORE BUFFER[2].x, IMM[0].xxxx, TEMP[0].zzzz\n"
- "AND TEMP[4], CONST[0].wwww, IMM[2].zzzz\n"
+ "AND TEMP[4], CONST[0][0].wwww, IMM[2].zzzz\n"
"UIF TEMP[4]\n"
"STORE BUFFER[2].y, IMM[0].xxxx, IMM[0].xxxx\n"
"ENDIF\n"
"NOT TEMP[4], TEMP[0].zzzz\n"
"UIF TEMP[4]\n"
/* Apply timestamp conversion */
- "AND TEMP[4], CONST[0].wwww, IMM[2].yyyy\n"
+ "AND TEMP[4], CONST[0][0].wwww, IMM[2].yyyy\n"
"UIF TEMP[4]\n"
"U64MUL TEMP[0].xy, TEMP[0], IMM[3].xyxy\n"
"U64DIV TEMP[0].xy, TEMP[0], IMM[3].zwzw\n"
"ENDIF\n"
/* Convert to boolean */
- "AND TEMP[4], CONST[0].wwww, IMM[1].wwww\n"
+ "AND TEMP[4], CONST[0][0].wwww, IMM[1].wwww\n"
"UIF TEMP[4]\n"
"U64SNE TEMP[0].x, TEMP[0].xyxy, IMM[4].zwzw\n"
"AND TEMP[0].x, TEMP[0].xxxx, IMM[1].xxxx\n"
"MOV TEMP[0].y, IMM[0].xxxx\n"
"ENDIF\n"
- "AND TEMP[4], CONST[0].wwww, IMM[2].zzzz\n"
+ "AND TEMP[4], CONST[0][0].wwww, IMM[2].zzzz\n"
"UIF TEMP[4]\n"
"STORE BUFFER[2].xy, IMM[0].xxxx, TEMP[0].xyxy\n"
"ELSE\n"
"MOV TEMP[0].x, IMM[0].wwww\n"
"ENDIF\n"
- "AND TEMP[4], CONST[0].wwww, IMM[2].wwww\n"
+ "AND TEMP[4], CONST[0][0].wwww, IMM[2].wwww\n"
"UIF TEMP[4]\n"
"UMIN TEMP[0].x, TEMP[0].xxxx, IMM[0].zzzz\n"
"ENDIF\n"
consts.config = 0;
if (index < 0)
consts.config |= 4;
- if (query->b.type == PIPE_QUERY_OCCLUSION_PREDICATE)
+ if (query->b.type == PIPE_QUERY_OCCLUSION_PREDICATE ||
+ query->b.type == PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE)
consts.config |= 8;
else if (query->b.type == PIPE_QUERY_SO_OVERFLOW_PREDICATE ||
query->b.type == PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE)
va = qbuf->buf->gpu_address + qbuf->results_end - query->result_size;
va += params.fence_offset;
- r600_gfx_wait_fence(rctx, va, 0x80000000, 0x80000000);
+ si_gfx_wait_fence(rctx, va, 0x80000000, 0x80000000);
}
rctx->b.launch_grid(&rctx->b, &grid);
{
struct r600_common_context *rctx = (struct r600_common_context *)ctx;
struct r600_query_hw *rquery = (struct r600_query_hw *)query;
- struct r600_query_buffer *qbuf;
struct r600_atom *atom = &rctx->render_cond_atom;
- /* Compute the size of SET_PREDICATION packets. */
- atom->num_dw = 0;
if (query) {
bool needs_workaround = false;
- /* There is a firmware regression in VI which causes successive
+ /* There was a firmware regression in VI which causes successive
* SET_PREDICATION packets to give the wrong answer for
* non-inverted stream overflow predication.
*/
- if (rctx->chip_class >= VI && !condition &&
+ if (((rctx->chip_class == VI && rctx->screen->info.pfp_fw_feature < 49) ||
+ (rctx->chip_class == GFX9 && rctx->screen->info.pfp_fw_feature < 38)) &&
+ !condition &&
(rquery->b.type == PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE ||
(rquery->b.type == PIPE_QUERY_SO_OVERFLOW_PREDICATE &&
(rquery->buffer.previous ||
ctx, query, true, PIPE_QUERY_TYPE_U64, 0,
&rquery->workaround_buf->b.b, rquery->workaround_offset);
- atom->num_dw = 5;
+ /* Settings this in the render cond atom is too late,
+ * so set it here. */
+ rctx->flags |= rctx->screen->barrier_flags.L2_to_cp |
+ R600_CONTEXT_FLUSH_FOR_RENDER_COND;
rctx->render_cond_force_off = old_force_off;
- } else {
- for (qbuf = &rquery->buffer; qbuf; qbuf = qbuf->previous)
- atom->num_dw += (qbuf->results_end / rquery->result_size) * 5;
-
- if (rquery->b.type == PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE)
- atom->num_dw *= R600_MAX_STREAMS;
}
}
rctx->set_atom_dirty(rctx, atom, query != NULL);
}
-void r600_suspend_queries(struct r600_common_context *ctx)
+void si_suspend_queries(struct r600_common_context *ctx)
{
struct r600_query_hw *query;
*/
num_dw += query->num_cs_dw_end;
}
- /* primitives generated query */
- num_dw += ctx->streamout.enable_atom.num_dw;
/* guess for ZPASS enable or PERFECT_ZPASS_COUNT enable updates */
num_dw += 13;
return num_dw;
}
-void r600_resume_queries(struct r600_common_context *ctx)
+void si_resume_queries(struct r600_common_context *ctx)
{
struct r600_query_hw *query;
unsigned num_cs_dw = r600_queries_num_cs_dw_for_resuming(ctx, &ctx->active_queries);
}
}
-/* Fix radeon_info::enabled_rb_mask for R600, R700, EVERGREEN, NI. */
-void r600_query_fix_enabled_rb_mask(struct r600_common_screen *rscreen)
-{
- struct r600_common_context *ctx =
- (struct r600_common_context*)rscreen->aux_context;
- struct radeon_winsys_cs *cs = ctx->gfx.cs;
- struct r600_resource *buffer;
- uint32_t *results;
- unsigned i, mask = 0;
- unsigned max_rbs = ctx->screen->info.num_render_backends;
-
- assert(rscreen->chip_class <= CAYMAN);
-
- /* if backend_map query is supported by the kernel */
- if (rscreen->info.r600_gb_backend_map_valid) {
- unsigned num_tile_pipes = rscreen->info.num_tile_pipes;
- unsigned backend_map = rscreen->info.r600_gb_backend_map;
- unsigned item_width, item_mask;
-
- if (ctx->chip_class >= EVERGREEN) {
- item_width = 4;
- item_mask = 0x7;
- } else {
- item_width = 2;
- item_mask = 0x3;
- }
-
- while (num_tile_pipes--) {
- i = backend_map & item_mask;
- mask |= (1<<i);
- backend_map >>= item_width;
- }
- if (mask != 0) {
- rscreen->info.enabled_rb_mask = mask;
- return;
- }
- }
-
- /* otherwise backup path for older kernels */
-
- /* create buffer for event data */
- buffer = (struct r600_resource*)
- pipe_buffer_create(ctx->b.screen, 0,
- PIPE_USAGE_STAGING, max_rbs * 16);
- if (!buffer)
- return;
-
- /* initialize buffer with zeroes */
- results = r600_buffer_map_sync_with_rings(ctx, buffer, PIPE_TRANSFER_WRITE);
- if (results) {
- memset(results, 0, max_rbs * 4 * 4);
-
- /* emit EVENT_WRITE for ZPASS_DONE */
- radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
- radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
- radeon_emit(cs, buffer->gpu_address);
- radeon_emit(cs, buffer->gpu_address >> 32);
-
- r600_emit_reloc(ctx, &ctx->gfx, buffer,
- RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
-
- /* analyze results */
- results = r600_buffer_map_sync_with_rings(ctx, buffer, PIPE_TRANSFER_READ);
- if (results) {
- for(i = 0; i < max_rbs; i++) {
- /* at least highest bit will be set if backend is used */
- if (results[i*4 + 1])
- mask |= (1<<i);
- }
- }
- }
-
- r600_resource_reference(&buffer, NULL);
-
- if (mask)
- rscreen->info.enabled_rb_mask = mask;
-}
-
#define XFULL(name_, query_type_, type_, result_type_, group_id_) \
{ \
.name = name_, \
X("GPU-surf-sync-busy", GPU_SURF_SYNC_BUSY, UINT64, AVERAGE),
X("GPU-cp-dma-busy", GPU_CP_DMA_BUSY, UINT64, AVERAGE),
X("GPU-scratch-ram-busy", GPU_SCRATCH_RAM_BUSY, UINT64, AVERAGE),
- X("GPU-ce-busy", GPU_CE_BUSY, UINT64, AVERAGE),
};
#undef X
if (!info) {
unsigned num_perfcounters =
- r600_get_perfcounter_info(rscreen, 0, NULL);
+ si_get_perfcounter_info(rscreen, 0, NULL);
return num_queries + num_perfcounters;
}
if (index >= num_queries)
- return r600_get_perfcounter_info(rscreen, index - num_queries, info);
+ return si_get_perfcounter_info(rscreen, index - num_queries, info);
*info = r600_driver_query_list[index];
return num_pc_groups + R600_NUM_SW_QUERY_GROUPS;
if (index < num_pc_groups)
- return r600_get_perfcounter_group_info(rscreen, index, info);
+ return si_get_perfcounter_group_info(rscreen, index, info);
index -= num_pc_groups;
if (index >= R600_NUM_SW_QUERY_GROUPS)
return 1;
}
-void r600_query_init(struct r600_common_context *rctx)
+void si_init_query_functions(struct r600_common_context *rctx)
{
rctx->b.create_query = r600_create_query;
- rctx->b.create_batch_query = r600_create_batch_query;
+ rctx->b.create_batch_query = si_create_batch_query;
rctx->b.destroy_query = r600_destroy_query;
rctx->b.begin_query = r600_begin_query;
rctx->b.end_query = r600_end_query;
LIST_INITHEAD(&rctx->active_queries);
}
-void r600_init_screen_query_functions(struct r600_common_screen *rscreen)
+void si_init_screen_query_functions(struct r600_common_screen *rscreen)
{
rscreen->b.get_driver_query_info = r600_get_driver_query_info;
rscreen->b.get_driver_query_group_info = r600_get_driver_query_group_info;
projects / mesa.git / blobdiff