winsys/amdgpu: remove the dcc_enable surface flag

[mesa.git] / src / gallium / drivers / radeon / r600_streamout.c

diff --git a/src/gallium/drivers/radeon/r600_streamout.c b/src/gallium/drivers/radeon/r600_streamout.c
index 815b641579caa90a43bd42034965da0fb7f707ba..33403b572af484e69ebe96853bbc06096f6dd65f 100644 (file)
--- a/src/gallium/drivers/radeon/r600_streamout.c
+++ b/src/gallium/drivers/radeon/r600_streamout.c
@@ -104,7 +104,7 @@ void r600_streamout_buffers_dirty(struct r600_common_context *rctx)
                (num_bufs - num_bufs_appended) * 6 + /* STRMOUT_BUFFER_UPDATE */
                (rctx->family > CHIP_R600 && rctx->family < CHIP_RS780 ? 2 : 0); /* SURFACE_BASE_UPDATE */
 
-       begin->dirty = true;
+       rctx->set_atom_dirty(rctx, begin, true);
 
        r600_set_streamout_enable(rctx, true);
 }
@@ -145,7 +145,7 @@ void r600_set_streamout_targets(struct pipe_context *ctx,
        if (num_targets) {
                r600_streamout_buffers_dirty(rctx);
        } else {
-               rctx->streamout.begin_atom.dirty = false;
+               rctx->set_atom_dirty(rctx, &rctx->streamout.begin_atom, false);
                r600_set_streamout_enable(rctx, false);
        }
 }
@@ -165,9 +165,9 @@ static void r600_flush_vgt_streamout(struct r600_common_context *rctx)
        }
 
        if (rctx->chip_class >= CIK) {
-               cik_write_uconfig_reg(cs, reg_strmout_cntl, 0);
+               radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
        } else {
-               r600_write_config_reg(cs, reg_strmout_cntl, 0);
+               radeon_set_config_reg(cs, reg_strmout_cntl, 0);
        }
 
        radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
@@ -201,7 +201,7 @@ static void r600_emit_streamout_begin(struct r600_common_context *rctx, struct r
                        /* SI binds streamout buffers as shader resources.
                         * VGT only counts primitives and tells the shader
                         * through SGPRs what to do. */
-                       r600_write_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
+                       radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
                        radeon_emit(cs, (t[i]->b.buffer_offset +
                                         t[i]->b.buffer_size) >> 2);    /* BUFFER_SIZE (in DW) */
                        radeon_emit(cs, stride_in_dw[i]);               /* VTX_STRIDE (in DW) */
@@ -210,14 +210,14 @@ static void r600_emit_streamout_begin(struct r600_common_context *rctx, struct r
 
                        update_flags |= SURFACE_BASE_UPDATE_STRMOUT(i);
 
-                       r600_write_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 3);
+                       radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 3);
                        radeon_emit(cs, (t[i]->b.buffer_offset +
                                         t[i]->b.buffer_size) >> 2);    /* BUFFER_SIZE (in DW) */
                        radeon_emit(cs, stride_in_dw[i]);               /* VTX_STRIDE (in DW) */
                        radeon_emit(cs, va >> 8);                       /* BUFFER_BASE */
 
                        r600_emit_reloc(rctx, &rctx->rings.gfx, r600_resource(t[i]->b.buffer),
-                                       RADEON_USAGE_WRITE, RADEON_PRIO_SHADER_RESOURCE_RW);
+                                       RADEON_USAGE_WRITE, RADEON_PRIO_RINGS_STREAMOUT);
 
                        /* R7xx requires this packet after updating BUFFER_BASE.
                         * Without this, R7xx locks up. */
@@ -227,7 +227,7 @@ static void r600_emit_streamout_begin(struct r600_common_context *rctx, struct r
                                radeon_emit(cs, va >> 8);
 
                                r600_emit_reloc(rctx, &rctx->rings.gfx, r600_resource(t[i]->b.buffer),
-                                               RADEON_USAGE_WRITE, RADEON_PRIO_SHADER_RESOURCE_RW);
+                                               RADEON_USAGE_WRITE, RADEON_PRIO_RINGS_STREAMOUT);
                        }
                }
 
@@ -245,7 +245,7 @@ static void r600_emit_streamout_begin(struct r600_common_context *rctx, struct r
                        radeon_emit(cs, va >> 32); /* src address hi */
 
                        r600_emit_reloc(rctx,  &rctx->rings.gfx, t[i]->buf_filled_size,
-                                       RADEON_USAGE_READ, RADEON_PRIO_MIN);
+                                       RADEON_USAGE_READ, RADEON_PRIO_SO_FILLED_SIZE);
                } else {
                        /* Start from the beginning. */
                        radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
@@ -289,13 +289,13 @@ void r600_emit_streamout_end(struct r600_common_context *rctx)
                radeon_emit(cs, 0); /* unused */
 
                r600_emit_reloc(rctx,  &rctx->rings.gfx, t[i]->buf_filled_size,
-                               RADEON_USAGE_WRITE, RADEON_PRIO_MIN);
+                               RADEON_USAGE_WRITE, RADEON_PRIO_SO_FILLED_SIZE);
 
                /* Zero the buffer size. The counters (primitives generated,
                 * primitives emitted) may be enabled even if there is not
                 * buffer bound. This ensures that the primitives-emitted query
                 * won't increment. */
-               r600_write_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
+               radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
 
                t[i]->buf_filled_size_valid = true;
        }
@@ -320,17 +320,24 @@ static bool r600_get_strmout_en(struct r600_common_context *rctx)
 static void r600_emit_streamout_enable(struct r600_common_context *rctx,
                                       struct r600_atom *atom)
 {
-       r600_write_context_reg(rctx->rings.gfx.cs,
-                              rctx->chip_class >= EVERGREEN ?
-                                      R_028B98_VGT_STRMOUT_BUFFER_CONFIG :
-                                      R_028B20_VGT_STRMOUT_BUFFER_EN,
-                              rctx->streamout.hw_enabled_mask);
-
-       r600_write_context_reg(rctx->rings.gfx.cs,
-                              rctx->chip_class >= EVERGREEN ?
-                                      R_028B94_VGT_STRMOUT_CONFIG :
-                                      R_028AB0_VGT_STRMOUT_EN,
-                              S_028B94_STREAMOUT_0_EN(r600_get_strmout_en(rctx)));
+       unsigned strmout_config_reg = R_028AB0_VGT_STRMOUT_EN;
+       unsigned strmout_config_val = S_028B94_STREAMOUT_0_EN(r600_get_strmout_en(rctx));
+       unsigned strmout_buffer_reg = R_028B20_VGT_STRMOUT_BUFFER_EN;
+       unsigned strmout_buffer_val = rctx->streamout.hw_enabled_mask &
+                                     rctx->streamout.enabled_stream_buffers_mask;
+
+       if (rctx->chip_class >= EVERGREEN) {
+               strmout_buffer_reg = R_028B98_VGT_STRMOUT_BUFFER_CONFIG;
+
+               strmout_config_reg = R_028B94_VGT_STRMOUT_CONFIG;
+               strmout_config_val |=
+                       S_028B94_RAST_STREAM(0) |
+                       S_028B94_STREAMOUT_1_EN(r600_get_strmout_en(rctx)) |
+                       S_028B94_STREAMOUT_2_EN(r600_get_strmout_en(rctx)) |
+                       S_028B94_STREAMOUT_3_EN(r600_get_strmout_en(rctx));
+       }
+       radeon_set_context_reg(rctx->rings.gfx.cs, strmout_buffer_reg, strmout_buffer_val);
+       radeon_set_context_reg(rctx->rings.gfx.cs, strmout_config_reg, strmout_config_val);
 }
 
 static void r600_set_streamout_enable(struct r600_common_context *rctx, bool enable)
@@ -339,10 +346,16 @@ static void r600_set_streamout_enable(struct r600_common_context *rctx, bool ena
        unsigned old_hw_enabled_mask = rctx->streamout.hw_enabled_mask;
 
        rctx->streamout.streamout_enabled = enable;
-       rctx->streamout.hw_enabled_mask = rctx->streamout.enabled_mask;
+
+       rctx->streamout.hw_enabled_mask = rctx->streamout.enabled_mask |
+                                         (rctx->streamout.enabled_mask << 4) |
+                                         (rctx->streamout.enabled_mask << 8) |
+                                         (rctx->streamout.enabled_mask << 12);
+
        if ((old_strmout_en != r600_get_strmout_en(rctx)) ||
-            (old_hw_enabled_mask != rctx->streamout.hw_enabled_mask))
-               rctx->streamout.enable_atom.dirty = true;
+            (old_hw_enabled_mask != rctx->streamout.hw_enabled_mask)) {
+               rctx->set_atom_dirty(rctx, &rctx->streamout.enable_atom, true);
+       }
 }
 
 void r600_update_prims_generated_query_state(struct r600_common_context *rctx,
@@ -357,8 +370,9 @@ void r600_update_prims_generated_query_state(struct r600_common_context *rctx,
                rctx->streamout.prims_gen_query_enabled =
                        rctx->streamout.num_prims_gen_queries != 0;
 
-               if (old_strmout_en != r600_get_strmout_en(rctx))
-                       rctx->streamout.enable_atom.dirty = true;
+               if (old_strmout_en != r600_get_strmout_en(rctx)) {
+                       rctx->set_atom_dirty(rctx, &rctx->streamout.enable_atom, true);
+               }
        }
 }