static int r600_setup_surface(struct pipe_screen *screen,
struct r600_texture *rtex,
- unsigned pitch_in_bytes_override)
+ unsigned pitch_in_bytes_override,
+ unsigned offset)
{
struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
+ unsigned i;
int r;
r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
rtex->surface.stencil_level[0].offset = rtex->surface.level[0].slice_size;
}
}
+
+ if (offset) {
+ for (i = 0; i < Elements(rtex->surface.level); ++i)
+ rtex->surface.level[i].offset += offset;
+ }
return 0;
}
-static boolean r600_texture_get_handle(struct pipe_screen* screen,
- struct pipe_resource *ptex,
- struct winsys_handle *whandle)
+static void r600_texture_init_metadata(struct r600_texture *rtex,
+ struct radeon_bo_metadata *metadata)
{
- struct r600_texture *rtex = (struct r600_texture*)ptex;
- struct r600_resource *resource = &rtex->resource;
struct radeon_surf *surface = &rtex->surface;
+
+ memset(metadata, 0, sizeof(*metadata));
+ metadata->microtile = surface->level[0].mode >= RADEON_SURF_MODE_1D ?
+ RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
+ metadata->macrotile = surface->level[0].mode >= RADEON_SURF_MODE_2D ?
+ RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
+ metadata->pipe_config = surface->pipe_config;
+ metadata->bankw = surface->bankw;
+ metadata->bankh = surface->bankh;
+ metadata->tile_split = surface->tile_split;
+ metadata->stencil_tile_split = surface->stencil_tile_split;
+ metadata->mtilea = surface->mtilea;
+ metadata->num_banks = surface->num_banks;
+ metadata->stride = surface->level[0].pitch_bytes;
+ metadata->scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
+}
+
+static void r600_dirty_all_framebuffer_states(struct r600_common_screen *rscreen)
+{
+ p_atomic_inc(&rscreen->dirty_fb_counter);
+}
+
+static void r600_eliminate_fast_color_clear(struct r600_common_screen *rscreen,
+ struct r600_texture *rtex)
+{
+ struct pipe_context *ctx = rscreen->aux_context;
+
+ pipe_mutex_lock(rscreen->aux_context_lock);
+ ctx->flush_resource(ctx, &rtex->resource.b.b);
+ ctx->flush(ctx, NULL, 0);
+ pipe_mutex_unlock(rscreen->aux_context_lock);
+}
+
+static void r600_texture_disable_cmask(struct r600_common_screen *rscreen,
+ struct r600_texture *rtex)
+{
+ if (!rtex->cmask.size)
+ return;
+
+ assert(rtex->resource.b.b.nr_samples <= 1);
+
+ /* Disable CMASK. */
+ memset(&rtex->cmask, 0, sizeof(rtex->cmask));
+ rtex->cmask.base_address_reg = rtex->resource.gpu_address >> 8;
+
+ if (rscreen->chip_class >= SI)
+ rtex->cb_color_info &= ~SI_S_028C70_FAST_CLEAR(1);
+ else
+ rtex->cb_color_info &= ~EG_S_028C70_FAST_CLEAR(1);
+
+ if (rtex->cmask_buffer != &rtex->resource)
+ pipe_resource_reference((struct pipe_resource**)&rtex->cmask_buffer, NULL);
+
+ /* Notify all contexts about the change. */
+ r600_dirty_all_framebuffer_states(rscreen);
+ p_atomic_inc(&rscreen->compressed_colortex_counter);
+}
+
+static void r600_texture_disable_dcc(struct r600_common_screen *rscreen,
+ struct r600_texture *rtex)
+{
+ struct r600_common_context *rctx =
+ (struct r600_common_context *)rscreen->aux_context;
+
+ if (!rtex->dcc_offset)
+ return;
+
+ /* Decompress DCC. */
+ pipe_mutex_lock(rscreen->aux_context_lock);
+ rctx->decompress_dcc(&rctx->b, rtex);
+ rctx->b.flush(&rctx->b, NULL, 0);
+ pipe_mutex_unlock(rscreen->aux_context_lock);
+
+ /* Disable DCC. */
+ rtex->dcc_offset = 0;
+ rtex->cb_color_info &= ~VI_S_028C70_DCC_ENABLE(1);
+
+ /* Notify all contexts about the change. */
+ r600_dirty_all_framebuffer_states(rscreen);
+}
+
+static boolean r600_texture_get_handle(struct pipe_screen* screen,
+ struct pipe_resource *resource,
+ struct winsys_handle *whandle,
+ unsigned usage)
+{
struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
+ struct r600_resource *res = (struct r600_resource*)resource;
+ struct r600_texture *rtex = (struct r600_texture*)resource;
+ struct radeon_bo_metadata metadata;
- rscreen->ws->buffer_set_tiling(resource->buf,
- NULL,
- surface->level[0].mode >= RADEON_SURF_MODE_1D ?
- RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
- surface->level[0].mode >= RADEON_SURF_MODE_2D ?
- RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
- surface->pipe_config,
- surface->bankw, surface->bankh,
- surface->tile_split,
- surface->stencil_tile_split,
- surface->mtilea, surface->num_banks,
- surface->level[0].pitch_bytes,
- (surface->flags & RADEON_SURF_SCANOUT) != 0);
-
- return rscreen->ws->buffer_get_handle(resource->buf,
- surface->level[0].pitch_bytes, whandle);
+ /* This is not supported now, but it might be required for OpenCL
+ * interop in the future.
+ */
+ if (resource->target != PIPE_BUFFER &&
+ (resource->nr_samples > 1 || rtex->is_depth))
+ return NULL;
+
+ if (!res->is_shared) {
+ res->is_shared = true;
+ res->external_usage = usage;
+
+ if (resource->target != PIPE_BUFFER) {
+ /* Since shader image stores don't support DCC on VI,
+ * disable it for external clients that want write
+ * access.
+ */
+ if (usage & PIPE_HANDLE_USAGE_WRITE)
+ r600_texture_disable_dcc(rscreen, rtex);
+
+ if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH)) {
+ /* Eliminate fast clear (both CMASK and DCC) */
+ r600_eliminate_fast_color_clear(rscreen, rtex);
+
+ /* Disable CMASK if flush_resource isn't going
+ * to be called.
+ */
+ r600_texture_disable_cmask(rscreen, rtex);
+ }
+
+ /* Set metadata. */
+ r600_texture_init_metadata(rtex, &metadata);
+ if (rscreen->query_opaque_metadata)
+ rscreen->query_opaque_metadata(rscreen, rtex,
+ &metadata);
+
+ rscreen->ws->buffer_set_metadata(res->buf, &metadata);
+ }
+ } else {
+ assert(res->external_usage == usage);
+ }
+
+ return rscreen->ws->buffer_get_handle(res->buf,
+ rtex->surface.level[0].pitch_bytes,
+ rtex->surface.level[0].offset,
+ whandle);
}
static void r600_texture_destroy(struct pipe_screen *screen,
if (rtex->cmask_buffer != &rtex->resource) {
pipe_resource_reference((struct pipe_resource**)&rtex->cmask_buffer, NULL);
}
- pipe_resource_reference((struct pipe_resource**)&rtex->dcc_buffer, NULL);
pb_reference(&resource->buf, NULL);
FREE(rtex);
}
unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height;
unsigned element_bits = 4;
unsigned cmask_cache_bits = 1024;
- unsigned num_pipes = rscreen->tiling_info.num_channels;
- unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
+ unsigned num_pipes = rscreen->info.num_tile_pipes;
+ unsigned pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;
struct r600_texture *rtex,
struct r600_cmask_info *out)
{
- unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
- unsigned num_pipes = rscreen->tiling_info.num_channels;
+ unsigned pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
+ unsigned num_pipes = rscreen->info.num_tile_pipes;
unsigned cl_width, cl_height;
switch (num_pipes) {
rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1);
else
rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
-}
-static void vi_texture_alloc_dcc_separate(struct r600_common_screen *rscreen,
- struct r600_texture *rtex)
-{
- if (rscreen->debug_flags & DBG_NO_DCC)
- return;
-
- rtex->dcc_buffer = (struct r600_resource *)
- r600_aligned_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
- PIPE_USAGE_DEFAULT, rtex->surface.dcc_size, rtex->surface.dcc_alignment);
- if (rtex->dcc_buffer == NULL) {
- return;
- }
-
- r600_screen_clear_buffer(rscreen, &rtex->dcc_buffer->b.b, 0, rtex->surface.dcc_size,
- 0xFFFFFFFF, true);
-
- rtex->cb_color_info |= VI_S_028C70_DCC_ENABLE(1);
+ p_atomic_inc(&rscreen->compressed_colortex_counter);
}
static unsigned r600_texture_get_htile_size(struct r600_common_screen *rscreen,
{
unsigned cl_width, cl_height, width, height;
unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
- unsigned num_pipes = rscreen->tiling_info.num_channels;
+ unsigned num_pipes = rscreen->info.num_tile_pipes;
if (rscreen->chip_class <= EVERGREEN &&
rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 26)
rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 38)
return 0;
+ /* Overalign HTILE on Stoney to fix piglit/depthstencil-render-miplevels 585. */
+ if (rscreen->family == CHIP_STONEY)
+ num_pipes = 4;
+
switch (num_pipes) {
case 1:
cl_width = 32;
slice_elements = (width * height) / (8 * 8);
slice_bytes = slice_elements * 4;
- pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
+ pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
base_align = num_pipes * pipe_interleave_bytes;
rtex->htile.pitch = width;
rtex->htile_buffer->buf->alignment, rtex->htile.pitch,
rtex->htile.height, rtex->htile.xalign, rtex->htile.yalign);
- if (rtex->dcc_buffer) {
- fprintf(f, " DCC: size=%u, alignment=%u\n",
- rtex->dcc_buffer->b.b.width0,
- rtex->dcc_buffer->buf->alignment);
+ if (rtex->dcc_offset) {
+ fprintf(f, " DCC: offset=%u, size=%"PRIu64", alignment=%"PRIu64"\n",
+ rtex->dcc_offset, rtex->surface.dcc_size,
+ rtex->surface.dcc_alignment);
for (i = 0; i <= rtex->surface.last_level; i++)
fprintf(f, " DCCLevel[%i]: offset=%"PRIu64"\n",
i, rtex->surface.level[i].dcc_offset);
r600_texture_create_object(struct pipe_screen *screen,
const struct pipe_resource *base,
unsigned pitch_in_bytes_override,
+ unsigned offset,
struct pb_buffer *buf,
struct radeon_surf *surface)
{
rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
rtex->surface = *surface;
- if (r600_setup_surface(screen, rtex, pitch_in_bytes_override)) {
+ if (r600_setup_surface(screen, rtex, pitch_in_bytes_override, offset)) {
FREE(rtex);
return NULL;
}
return NULL;
}
}
- if (rtex->surface.dcc_size)
- vi_texture_alloc_dcc_separate(rscreen, rtex);
+
+ if (!buf && rtex->surface.dcc_size &&
+ !(rscreen->debug_flags & DBG_NO_DCC)) {
+ /* Reserve space for the DCC buffer. */
+ rtex->dcc_offset = align(rtex->size, rtex->surface.dcc_alignment);
+ rtex->size = rtex->dcc_offset + rtex->surface.dcc_size;
+ rtex->cb_color_info |= VI_S_028C70_DCC_ENABLE(1);
+ }
}
/* Now create the backing buffer. */
}
} else {
resource->buf = buf;
- resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf);
- resource->gpu_address = rscreen->ws->buffer_get_virtual_address(resource->cs_buf);
- resource->domains = rscreen->ws->buffer_get_initial_domain(resource->cs_buf);
+ resource->gpu_address = rscreen->ws->buffer_get_virtual_address(resource->buf);
+ resource->domains = rscreen->ws->buffer_get_initial_domain(resource->buf);
}
if (rtex->cmask.size) {
rtex->cmask.offset, rtex->cmask.size,
0xCCCCCCCC, true);
}
+ if (rtex->dcc_offset) {
+ r600_screen_clear_buffer(rscreen, &rtex->resource.b.b,
+ rtex->dcc_offset,
+ rtex->surface.dcc_size,
+ 0xFFFFFFFF, true);
+ }
/* Initialize the CMASK base register value. */
rtex->cmask.base_address_reg =
if (r) {
return NULL;
}
- return (struct pipe_resource *)r600_texture_create_object(screen, templ,
+ return (struct pipe_resource *)r600_texture_create_object(screen, templ, 0,
0, NULL, &surface);
}
static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
const struct pipe_resource *templ,
- struct winsys_handle *whandle)
+ struct winsys_handle *whandle,
+ unsigned usage)
{
struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
struct pb_buffer *buf = NULL;
- unsigned stride = 0;
+ unsigned stride = 0, offset = 0;
unsigned array_mode;
- enum radeon_bo_layout micro, macro;
struct radeon_surf surface;
- bool scanout;
int r;
+ struct radeon_bo_metadata metadata = {};
+ struct r600_texture *rtex;
/* Support only 2D textures without mipmaps */
if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
templ->depth0 != 1 || templ->last_level != 0)
return NULL;
- buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride);
+ buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride, &offset);
if (!buf)
return NULL;
- rscreen->ws->buffer_get_tiling(buf, µ, ¯o,
- &surface.bankw, &surface.bankh,
- &surface.tile_split,
- &surface.stencil_tile_split,
- &surface.mtilea, &scanout);
+ rscreen->ws->buffer_get_metadata(buf, &metadata);
+
+ surface.bankw = metadata.bankw;
+ surface.bankh = metadata.bankh;
+ surface.tile_split = metadata.tile_split;
+ surface.stencil_tile_split = metadata.stencil_tile_split;
+ surface.mtilea = metadata.mtilea;
- if (macro == RADEON_LAYOUT_TILED)
+ if (metadata.macrotile == RADEON_LAYOUT_TILED)
array_mode = RADEON_SURF_MODE_2D;
- else if (micro == RADEON_LAYOUT_TILED)
+ else if (metadata.microtile == RADEON_LAYOUT_TILED)
array_mode = RADEON_SURF_MODE_1D;
else
array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
return NULL;
}
- if (scanout)
+ if (metadata.scanout)
surface.flags |= RADEON_SURF_SCANOUT;
- return (struct pipe_resource *)r600_texture_create_object(screen, templ,
- stride, buf, &surface);
+ rtex = r600_texture_create_object(screen, templ, stride,
+ offset, buf, &surface);
+ if (!rtex)
+ return NULL;
+
+ rtex->resource.is_shared = true;
+ rtex->resource.external_usage = usage;
+ return &rtex->resource.b.b;
}
bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
/* Untiled buffers in VRAM, which is slow for CPU reads */
use_staging_texture = TRUE;
} else if (!(usage & PIPE_TRANSFER_READ) &&
- (r600_rings_is_buffer_referenced(rctx, rtex->resource.cs_buf, RADEON_USAGE_READWRITE) ||
+ (r600_rings_is_buffer_referenced(rctx, rtex->resource.buf, RADEON_USAGE_READWRITE) ||
!rctx->ws->buffer_wait(rtex->resource.buf, 0, RADEON_USAGE_READWRITE))) {
/* Use a staging texture for uploads if the underlying BO is busy. */
use_staging_texture = TRUE;
const struct pipe_surface *templ)
{
unsigned level = templ->u.tex.level;
+ unsigned width = u_minify(tex->width0, level);
+ unsigned height = u_minify(tex->height0, level);
+
+ if (tex->target != PIPE_BUFFER && templ->format != tex->format) {
+ const struct util_format_description *tex_desc
+ = util_format_description(tex->format);
+ const struct util_format_description *templ_desc
+ = util_format_description(templ->format);
+
+ assert(tex_desc->block.bits == templ_desc->block.bits);
+
+ /* Adjust size of surface if and only if the block width or
+ * height is changed. */
+ if (tex_desc->block.width != templ_desc->block.width ||
+ tex_desc->block.height != templ_desc->block.height) {
+ unsigned nblks_x = util_format_get_nblocksx(tex->format, width);
+ unsigned nblks_y = util_format_get_nblocksy(tex->format, height);
+
+ width = nblks_x * templ_desc->block.width;
+ height = nblks_y * templ_desc->block.height;
+ }
+ }
- return r600_create_surface_custom(pipe, tex, templ,
- u_minify(tex->width0, level),
- u_minify(tex->height0, level));
+ return r600_create_surface_custom(pipe, tex, templ, width, height);
}
static void r600_surface_destroy(struct pipe_context *pipe,
return V_0280A0_SWAP_STD_REV; /* WZYX */
else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X))
return V_0280A0_SWAP_ALT; /* ZYXW */
- else if (HAS_SWIZZLE(1,X) && HAS_SWIZZLE(2,Y))
- return V_0280A0_SWAP_ALT_REV; /* WXYZ */
+ else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,W))
+ return V_0280A0_SWAP_ALT_REV; /* YZWX */
break;
}
return ~0U;
{
int i;
+ /* This function is broken in BE, so just disable this path for now */
+#ifdef PIPE_ARCH_BIG_ENDIAN
+ return;
+#endif
+
if (rctx->render_cond)
return;
for (i = 0; i < fb->nr_cbufs; i++) {
- struct r600_surface *surf;
struct r600_texture *tex;
unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
if (!(*buffers & clear_bit))
continue;
- surf = (struct r600_surface *)fb->cbufs[i];
tex = (struct r600_texture *)fb->cbufs[i]->texture;
/* 128-bit formats are unusupported */
continue;
}
+ /* shared textures can't use fast clear without an explicit flush,
+ * because there is no way to communicate the clear color among
+ * all clients
+ */
+ if (tex->resource.is_shared &&
+ !(tex->resource.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
+ continue;
+
/* fast color clear with 1D tiling doesn't work on old kernels and CIK */
if (tex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
rctx->chip_class >= CIK &&
continue;
}
- if (tex->dcc_buffer) {
+ if (tex->dcc_offset) {
uint32_t reset_value;
bool clear_words_needed;
vi_get_fast_clear_parameters(fb->cbufs[i]->format, color, &reset_value, &clear_words_needed);
- rctx->clear_buffer(&rctx->b, &tex->dcc_buffer->b.b,
- 0, tex->surface.dcc_size, reset_value, true);
+ rctx->clear_buffer(&rctx->b, &tex->resource.b.b,
+ tex->dcc_offset, tex->surface.dcc_size,
+ reset_value, true);
if (clear_words_needed)
tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
} else {
- /* RB+ doesn't work with CMASK fast clear. */
- if (surf->sx_ps_downconvert)
+ /* Stoney/RB+ doesn't work with CMASK fast clear. */
+ if (rctx->family == CHIP_STONEY)
continue;
/* ensure CMASK is enabled */
projects / mesa.git / blobdiff