gallium/radeon: just get num_tile_pipes from the winsys

[mesa.git] / src / gallium / drivers / radeon / r600_texture.c

diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index 6515a829b5aa3cf84595e7165700c3ae283cf5c3..9d91e64ed30088bd13620a3418d6ac745c9ce3c6 100644 (file)
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -361,7 +361,7 @@ void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
        unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height;
        unsigned element_bits = 4;
        unsigned cmask_cache_bits = 1024;
-       unsigned num_pipes = rscreen->tiling_info.num_channels;
+       unsigned num_pipes = rscreen->info.num_tile_pipes;
        unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
 
        unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
@@ -395,7 +395,7 @@ static void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
                                      struct r600_cmask_info *out)
 {
        unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
-       unsigned num_pipes = rscreen->tiling_info.num_channels;
+       unsigned num_pipes = rscreen->info.num_tile_pipes;
        unsigned cl_width, cl_height;
 
        switch (num_pipes) {
@@ -515,7 +515,7 @@ static unsigned r600_texture_get_htile_size(struct r600_common_screen *rscreen,
 {
        unsigned cl_width, cl_height, width, height;
        unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
-       unsigned num_pipes = rscreen->tiling_info.num_channels;
+       unsigned num_pipes = rscreen->info.num_tile_pipes;
 
        if (rscreen->chip_class <= EVERGREEN &&
            rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 26)
@@ -533,6 +533,10 @@ static unsigned r600_texture_get_htile_size(struct r600_common_screen *rscreen,
            rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 38)
                return 0;
 
+       /* Overalign HTILE on Stoney to fix piglit/depthstencil-render-miplevels 585. */
+       if (rscreen->family == CHIP_STONEY)
+               num_pipes = 4;
+
        switch (num_pipes) {
        case 1:
                cl_width = 32;
@@ -754,9 +758,8 @@ r600_texture_create_object(struct pipe_screen *screen,
                }
        } else {
                resource->buf = buf;
-               resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf);
-               resource->gpu_address = rscreen->ws->buffer_get_virtual_address(resource->cs_buf);
-               resource->domains = rscreen->ws->buffer_get_initial_domain(resource->cs_buf);
+               resource->gpu_address = rscreen->ws->buffer_get_virtual_address(resource->buf);
+               resource->domains = rscreen->ws->buffer_get_initial_domain(resource->buf);
        }
 
        if (rtex->cmask.size) {
@@ -1024,7 +1027,7 @@ static void *r600_texture_transfer_map(struct pipe_context *ctx,
                /* Untiled buffers in VRAM, which is slow for CPU reads */
                use_staging_texture = TRUE;
        } else if (!(usage & PIPE_TRANSFER_READ) &&
-           (r600_rings_is_buffer_referenced(rctx, rtex->resource.cs_buf, RADEON_USAGE_READWRITE) ||
+           (r600_rings_is_buffer_referenced(rctx, rtex->resource.buf, RADEON_USAGE_READWRITE) ||
             !rctx->ws->buffer_wait(rtex->resource.buf, 0, RADEON_USAGE_READWRITE))) {
                /* Use a staging texture for uploads if the underlying BO is busy. */
                use_staging_texture = TRUE;
@@ -1213,10 +1216,30 @@ static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
                                                const struct pipe_surface *templ)
 {
        unsigned level = templ->u.tex.level;
+       unsigned width = u_minify(tex->width0, level);
+       unsigned height = u_minify(tex->height0, level);
+
+       if (templ->format != tex->format) {
+               const struct util_format_description *tex_desc
+                       = util_format_description(tex->format);
+               const struct util_format_description *templ_desc
+                       = util_format_description(templ->format);
+
+               assert(tex_desc->block.bits == templ_desc->block.bits);
+
+               /* Adjust size of surface if and only if the block width or
+                * height is changed. */
+               if (tex_desc->block.width != templ_desc->block.width ||
+                   tex_desc->block.height != templ_desc->block.height) {
+                       unsigned nblks_x = util_format_get_nblocksx(tex->format, width);
+                       unsigned nblks_y = util_format_get_nblocksy(tex->format, height);
+
+                       width = nblks_x * templ_desc->block.width;
+                       height = nblks_y * templ_desc->block.height;
+               }
+       }
 
-       return r600_create_surface_custom(pipe, tex, templ,
-                                         u_minify(tex->width0, level),
-                                         u_minify(tex->height0, level));
+       return r600_create_surface_custom(pipe, tex, templ, width, height);
 }
 
 static void r600_surface_destroy(struct pipe_context *pipe,
@@ -1445,6 +1468,10 @@ void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
                        if (clear_words_needed)
                                tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
                } else {
+                       /* Stoney/RB+ doesn't work with CMASK fast clear. */
+                       if (rctx->family == CHIP_STONEY)
+                               continue;
+
                        /* ensure CMASK is enabled */
                        r600_texture_alloc_cmask_separate(rctx->screen, tex);
                        if (tex->cmask.size == 0) {