/*
* Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
-#include "r600_pipe_common.h"
+
+#include "radeonsi/si_pipe.h"
#include "r600_cs.h"
#include "r600_query.h"
#include "util/u_format.h"
#include "util/u_log.h"
#include "util/u_memory.h"
#include "util/u_pack_color.h"
+#include "util/u_resource.h"
#include "util/u_surface.h"
#include "util/os_time.h"
#include <errno.h>
#include "state_tracker/drm_driver.h"
#include "amd/common/sid.h"
-static void r600_texture_discard_cmask(struct r600_common_screen *rscreen,
- struct r600_texture *rtex);
static enum radeon_surf_mode
-r600_choose_tiling(struct r600_common_screen *rscreen,
+r600_choose_tiling(struct si_screen *sscreen,
const struct pipe_resource *templ);
-bool si_prepare_for_dma_blit(struct r600_common_context *rctx,
+bool si_prepare_for_dma_blit(struct si_context *sctx,
struct r600_texture *rdst,
unsigned dst_level, unsigned dstx,
unsigned dsty, unsigned dstz,
unsigned src_level,
const struct pipe_box *src_box)
{
- if (!rctx->dma.cs)
+ if (!sctx->b.dma_cs)
return false;
if (rdst->surface.bpe != rsrc->surface.bpe)
src_box->height, src_box->depth))
return false;
- r600_texture_discard_cmask(rctx->screen, rdst);
+ si_texture_discard_cmask(sctx->screen, rdst);
}
/* All requirements are met. Prepare textures for SDMA. */
if (rsrc->cmask.size && rsrc->dirty_level_mask & (1 << src_level))
- rctx->b.flush_resource(&rctx->b, &rsrc->resource.b.b);
+ sctx->b.b.flush_resource(&sctx->b.b, &rsrc->resource.b.b);
assert(!(rsrc->dirty_level_mask & (1 << src_level)));
assert(!(rdst->dirty_level_mask & (1 << dst_level)));
/* Copy from a full GPU texture to a transfer's staging one. */
static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
{
- struct r600_common_context *rctx = (struct r600_common_context*)ctx;
+ struct si_context *sctx = (struct si_context*)ctx;
struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
struct pipe_resource *dst = &rtransfer->staging->b.b;
struct pipe_resource *src = transfer->resource;
return;
}
- rctx->dma_copy(ctx, dst, 0, 0, 0, 0, src, transfer->level,
+ sctx->b.dma_copy(ctx, dst, 0, 0, 0, 0, src, transfer->level,
&transfer->box);
}
/* Copy from a transfer's staging texture to a full GPU one. */
static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
{
- struct r600_common_context *rctx = (struct r600_common_context*)ctx;
+ struct si_context *sctx = (struct si_context*)ctx;
struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
struct pipe_resource *dst = transfer->resource;
struct pipe_resource *src = &rtransfer->staging->b.b;
return;
}
- rctx->dma_copy(ctx, dst, transfer->level,
+ sctx->b.dma_copy(ctx, dst, transfer->level,
transfer->box.x, transfer->box.y, transfer->box.z,
src, 0, &sbox);
}
-static unsigned r600_texture_get_offset(struct r600_common_screen *rscreen,
+static unsigned r600_texture_get_offset(struct si_screen *sscreen,
struct r600_texture *rtex, unsigned level,
const struct pipe_box *box,
unsigned *stride,
unsigned *layer_stride)
{
- if (rscreen->chip_class >= GFX9) {
+ if (sscreen->info.chip_class >= GFX9) {
*stride = rtex->surface.u.gfx9.surf_pitch * rtex->surface.bpe;
*layer_stride = rtex->surface.u.gfx9.surf_slice_size;
}
}
-static int r600_init_surface(struct r600_common_screen *rscreen,
+static int r600_init_surface(struct si_screen *sscreen,
struct radeon_surf *surface,
const struct pipe_resource *ptex,
enum radeon_surf_mode array_mode,
bpe = 4; /* stencil is allocated separately on evergreen */
} else {
bpe = util_format_get_blocksize(ptex->format);
- assert(util_is_power_of_two(bpe));
+ assert(util_is_power_of_two_or_zero(bpe));
}
if (!is_flushed_depth && is_depth) {
flags |= RADEON_SURF_ZBUFFER;
if (tc_compatible_htile &&
- (rscreen->chip_class >= GFX9 ||
+ (sscreen->info.chip_class >= GFX9 ||
array_mode == RADEON_SURF_MODE_2D)) {
/* TC-compatible HTILE only supports Z32_FLOAT.
* GFX9 also supports Z16_UNORM.
* On VI, promote Z16 to Z32. DB->CB copies will convert
* the format for transfers.
*/
- if (rscreen->chip_class == VI)
+ if (sscreen->info.chip_class == VI)
bpe = 4;
flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
flags |= RADEON_SURF_SBUFFER;
}
- if (rscreen->chip_class >= VI &&
+ if (sscreen->info.chip_class >= VI &&
(ptex->flags & R600_RESOURCE_FLAG_DISABLE_DCC ||
ptex->format == PIPE_FORMAT_R9G9B9E5_FLOAT ||
/* DCC MSAA array textures are disallowed due to incomplete clear impl. */
(ptex->nr_samples >= 2 &&
- (!rscreen->dcc_msaa_allowed || ptex->array_size > 1))))
+ (!sscreen->dcc_msaa_allowed || ptex->array_size > 1))))
flags |= RADEON_SURF_DISABLE_DCC;
if (ptex->bind & PIPE_BIND_SCANOUT || is_scanout) {
if (!(ptex->flags & R600_RESOURCE_FLAG_FORCE_TILING))
flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
- r = rscreen->ws->surface_init(rscreen->ws, ptex, flags, bpe,
+ r = sscreen->ws->surface_init(sscreen->ws, ptex, flags, bpe,
array_mode, surface);
if (r) {
return r;
}
- if (rscreen->chip_class >= GFX9) {
- assert(!pitch_in_bytes_override ||
- pitch_in_bytes_override == surface->u.gfx9.surf_pitch * bpe);
+ unsigned pitch = pitch_in_bytes_override / bpe;
+
+ if (sscreen->info.chip_class >= GFX9) {
+ if (pitch) {
+ surface->u.gfx9.surf_pitch = pitch;
+ surface->u.gfx9.surf_slice_size =
+ (uint64_t)pitch * surface->u.gfx9.surf_height * bpe;
+ }
surface->u.gfx9.surf_offset = offset;
} else {
+ if (pitch) {
+ surface->u.legacy.level[0].nblk_x = pitch;
+ surface->u.legacy.level[0].slice_size_dw =
+ ((uint64_t)pitch * surface->u.legacy.level[0].nblk_y * bpe) / 4;
+ }
if (offset) {
for (i = 0; i < ARRAY_SIZE(surface->u.legacy.level); ++i)
surface->u.legacy.level[i].offset += offset;
return 0;
}
-static void r600_texture_init_metadata(struct r600_common_screen *rscreen,
+static void r600_texture_init_metadata(struct si_screen *sscreen,
struct r600_texture *rtex,
struct radeon_bo_metadata *metadata)
{
memset(metadata, 0, sizeof(*metadata));
- if (rscreen->chip_class >= GFX9) {
+ if (sscreen->info.chip_class >= GFX9) {
metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
} else {
metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
}
}
-static void r600_surface_import_metadata(struct r600_common_screen *rscreen,
+static void r600_surface_import_metadata(struct si_screen *sscreen,
struct radeon_surf *surf,
struct radeon_bo_metadata *metadata,
enum radeon_surf_mode *array_mode,
bool *is_scanout)
{
- if (rscreen->chip_class >= GFX9) {
+ if (sscreen->info.chip_class >= GFX9) {
if (metadata->u.gfx9.swizzle_mode > 0)
*array_mode = RADEON_SURF_MODE_2D;
else
}
}
-static void r600_eliminate_fast_color_clear(struct r600_common_context *rctx,
- struct r600_texture *rtex)
+void si_eliminate_fast_color_clear(struct si_context *sctx,
+ struct r600_texture *rtex)
{
- struct r600_common_screen *rscreen = rctx->screen;
- struct pipe_context *ctx = &rctx->b;
+ struct si_screen *sscreen = sctx->screen;
+ struct pipe_context *ctx = &sctx->b.b;
- if (ctx == rscreen->aux_context)
- mtx_lock(&rscreen->aux_context_lock);
+ if (ctx == sscreen->aux_context)
+ mtx_lock(&sscreen->aux_context_lock);
+ unsigned n = sctx->b.num_decompress_calls;
ctx->flush_resource(ctx, &rtex->resource.b.b);
- ctx->flush(ctx, NULL, 0);
- if (ctx == rscreen->aux_context)
- mtx_unlock(&rscreen->aux_context_lock);
+ /* Flush only if any fast clear elimination took place. */
+ if (n != sctx->b.num_decompress_calls)
+ ctx->flush(ctx, NULL, 0);
+
+ if (ctx == sscreen->aux_context)
+ mtx_unlock(&sscreen->aux_context_lock);
}
-static void r600_texture_discard_cmask(struct r600_common_screen *rscreen,
- struct r600_texture *rtex)
+void si_texture_discard_cmask(struct si_screen *sscreen,
+ struct r600_texture *rtex)
{
if (!rtex->cmask.size)
return;
r600_resource_reference(&rtex->cmask_buffer, NULL);
/* Notify all contexts about the change. */
- p_atomic_inc(&rscreen->dirty_tex_counter);
- p_atomic_inc(&rscreen->compressed_colortex_counter);
+ p_atomic_inc(&sscreen->dirty_tex_counter);
+ p_atomic_inc(&sscreen->compressed_colortex_counter);
}
static bool r600_can_disable_dcc(struct r600_texture *rtex)
!(rtex->resource.external_usage & PIPE_HANDLE_USAGE_WRITE));
}
-static bool r600_texture_discard_dcc(struct r600_common_screen *rscreen,
+static bool r600_texture_discard_dcc(struct si_screen *sscreen,
struct r600_texture *rtex)
{
if (!r600_can_disable_dcc(rtex))
rtex->dcc_offset = 0;
/* Notify all contexts about the change. */
- p_atomic_inc(&rscreen->dirty_tex_counter);
+ p_atomic_inc(&sscreen->dirty_tex_counter);
return true;
}
* context 1 & 2 read garbage, because DCC is disabled, yet there are
* compressed tiled
*
- * \param rctx the current context if you have one, or rscreen->aux_context
+ * \param sctx the current context if you have one, or rscreen->aux_context
* if you don't.
*/
-bool si_texture_disable_dcc(struct r600_common_context *rctx,
+bool si_texture_disable_dcc(struct si_context *sctx,
struct r600_texture *rtex)
{
- struct r600_common_screen *rscreen = rctx->screen;
+ struct si_screen *sscreen = sctx->screen;
if (!r600_can_disable_dcc(rtex))
return false;
- if (&rctx->b == rscreen->aux_context)
- mtx_lock(&rscreen->aux_context_lock);
+ if (&sctx->b.b == sscreen->aux_context)
+ mtx_lock(&sscreen->aux_context_lock);
/* Decompress DCC. */
- rctx->decompress_dcc(&rctx->b, rtex);
- rctx->b.flush(&rctx->b, NULL, 0);
+ si_decompress_dcc(&sctx->b.b, rtex);
+ sctx->b.b.flush(&sctx->b.b, NULL, 0);
- if (&rctx->b == rscreen->aux_context)
- mtx_unlock(&rscreen->aux_context_lock);
+ if (&sctx->b.b == sscreen->aux_context)
+ mtx_unlock(&sscreen->aux_context_lock);
- return r600_texture_discard_dcc(rscreen, rtex);
+ return r600_texture_discard_dcc(sscreen, rtex);
}
-static void r600_reallocate_texture_inplace(struct r600_common_context *rctx,
+static void r600_reallocate_texture_inplace(struct si_context *sctx,
struct r600_texture *rtex,
unsigned new_bind_flag,
bool invalidate_storage)
{
- struct pipe_screen *screen = rctx->b.screen;
+ struct pipe_screen *screen = sctx->b.b.screen;
struct r600_texture *new_tex;
struct pipe_resource templ = rtex->resource.b.b;
unsigned i;
return;
/* This fails with MSAA, depth, and compressed textures. */
- if (r600_choose_tiling(rctx->screen, &templ) !=
+ if (r600_choose_tiling(sctx->screen, &templ) !=
RADEON_SURF_MODE_LINEAR_ALIGNED)
return;
}
u_box_3d(0, 0, 0,
u_minify(templ.width0, i), u_minify(templ.height0, i),
- util_max_layer(&templ, i) + 1, &box);
+ util_num_layers(&templ, i), &box);
- rctx->dma_copy(&rctx->b, &new_tex->resource.b.b, i, 0, 0, 0,
+ sctx->b.dma_copy(&sctx->b.b, &new_tex->resource.b.b, i, 0, 0, 0,
&rtex->resource.b.b, i, &box);
}
}
if (new_bind_flag == PIPE_BIND_LINEAR) {
- r600_texture_discard_cmask(rctx->screen, rtex);
- r600_texture_discard_dcc(rctx->screen, rtex);
+ si_texture_discard_cmask(sctx->screen, rtex);
+ r600_texture_discard_dcc(sctx->screen, rtex);
}
/* Replace the structure fields of rtex. */
r600_texture_reference(&new_tex, NULL);
- p_atomic_inc(&rctx->screen->dirty_tex_counter);
+ p_atomic_inc(&sctx->screen->dirty_tex_counter);
+}
+
+static uint32_t si_get_bo_metadata_word1(struct si_screen *sscreen)
+{
+ return (ATI_VENDOR_ID << 16) | sscreen->info.pci_id;
+}
+
+static void si_query_opaque_metadata(struct si_screen *sscreen,
+ struct r600_texture *rtex,
+ struct radeon_bo_metadata *md)
+{
+ struct pipe_resource *res = &rtex->resource.b.b;
+ static const unsigned char swizzle[] = {
+ PIPE_SWIZZLE_X,
+ PIPE_SWIZZLE_Y,
+ PIPE_SWIZZLE_Z,
+ PIPE_SWIZZLE_W
+ };
+ uint32_t desc[8], i;
+ bool is_array = util_texture_is_array(res->target);
+
+ /* DRM 2.x.x doesn't support this. */
+ if (sscreen->info.drm_major != 3)
+ return;
+
+ assert(rtex->dcc_separate_buffer == NULL);
+ assert(rtex->fmask.size == 0);
+
+ /* Metadata image format format version 1:
+ * [0] = 1 (metadata format identifier)
+ * [1] = (VENDOR_ID << 16) | PCI_ID
+ * [2:9] = image descriptor for the whole resource
+ * [2] is always 0, because the base address is cleared
+ * [9] is the DCC offset bits [39:8] from the beginning of
+ * the buffer
+ * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
+ */
+
+ md->metadata[0] = 1; /* metadata image format version 1 */
+
+ /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
+ md->metadata[1] = si_get_bo_metadata_word1(sscreen);
+
+ si_make_texture_descriptor(sscreen, rtex, true,
+ res->target, res->format,
+ swizzle, 0, res->last_level, 0,
+ is_array ? res->array_size - 1 : 0,
+ res->width0, res->height0, res->depth0,
+ desc, NULL);
+
+ si_set_mutable_tex_desc_fields(sscreen, rtex, &rtex->surface.u.legacy.level[0],
+ 0, 0, rtex->surface.blk_w, false, desc);
+
+ /* Clear the base address and set the relative DCC offset. */
+ desc[0] = 0;
+ desc[1] &= C_008F14_BASE_ADDRESS_HI;
+ desc[7] = rtex->dcc_offset >> 8;
+
+ /* Dwords [2:9] contain the image descriptor. */
+ memcpy(&md->metadata[2], desc, sizeof(desc));
+ md->size_metadata = 10 * 4;
+
+ /* Dwords [10:..] contain the mipmap level offsets. */
+ if (sscreen->info.chip_class <= VI) {
+ for (i = 0; i <= res->last_level; i++)
+ md->metadata[10+i] = rtex->surface.u.legacy.level[i].offset >> 8;
+
+ md->size_metadata += (1 + res->last_level) * 4;
+ }
+}
+
+static void si_apply_opaque_metadata(struct si_screen *sscreen,
+ struct r600_texture *rtex,
+ struct radeon_bo_metadata *md)
+{
+ uint32_t *desc = &md->metadata[2];
+
+ if (sscreen->info.chip_class < VI)
+ return;
+
+ /* Return if DCC is enabled. The texture should be set up with it
+ * already.
+ */
+ if (md->size_metadata >= 10 * 4 && /* at least 2(header) + 8(desc) dwords */
+ md->metadata[0] != 0 &&
+ md->metadata[1] == si_get_bo_metadata_word1(sscreen) &&
+ G_008F28_COMPRESSION_EN(desc[6])) {
+ rtex->dcc_offset = (uint64_t)desc[7] << 8;
+ return;
+ }
+
+ /* Disable DCC. These are always set by texture_from_handle and must
+ * be cleared here.
+ */
+ rtex->dcc_offset = 0;
}
static boolean r600_texture_get_handle(struct pipe_screen* screen,
struct winsys_handle *whandle,
unsigned usage)
{
- struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
- struct r600_common_context *rctx;
+ struct si_screen *sscreen = (struct si_screen*)screen;
+ struct si_context *sctx;
struct r600_resource *res = (struct r600_resource*)resource;
struct r600_texture *rtex = (struct r600_texture*)resource;
struct radeon_bo_metadata metadata;
bool update_metadata = false;
unsigned stride, offset, slice_size;
+ bool flush = false;
ctx = threaded_context_unwrap_sync(ctx);
- rctx = (struct r600_common_context*)(ctx ? ctx : rscreen->aux_context);
+ sctx = (struct si_context*)(ctx ? ctx : sscreen->aux_context);
if (resource->target != PIPE_BUFFER) {
/* This is not supported now, but it might be required for OpenCL
return false;
/* Move a suballocated texture into a non-suballocated allocation. */
- if (rscreen->ws->buffer_is_suballocated(res->buf) ||
+ if (sscreen->ws->buffer_is_suballocated(res->buf) ||
rtex->surface.tile_swizzle ||
(rtex->resource.flags & RADEON_FLAG_NO_INTERPROCESS_SHARING &&
+ sscreen->info.has_local_buffers &&
whandle->type != DRM_API_HANDLE_TYPE_KMS)) {
assert(!res->b.is_shared);
- r600_reallocate_texture_inplace(rctx, rtex,
+ r600_reallocate_texture_inplace(sctx, rtex,
PIPE_BIND_SHARED, false);
- rctx->b.flush(&rctx->b, NULL, 0);
+ flush = true;
assert(res->b.b.bind & PIPE_BIND_SHARED);
assert(res->flags & RADEON_FLAG_NO_SUBALLOC);
assert(!(res->flags & RADEON_FLAG_NO_INTERPROCESS_SHARING));
* access.
*/
if (usage & PIPE_HANDLE_USAGE_WRITE && rtex->dcc_offset) {
- if (si_texture_disable_dcc(rctx, rtex))
+ if (si_texture_disable_dcc(sctx, rtex)) {
update_metadata = true;
+ /* si_texture_disable_dcc flushes the context */
+ flush = false;
+ }
}
if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) &&
(rtex->cmask.size || rtex->dcc_offset)) {
/* Eliminate fast clear (both CMASK and DCC) */
- r600_eliminate_fast_color_clear(rctx, rtex);
+ si_eliminate_fast_color_clear(sctx, rtex);
+ /* eliminate_fast_color_clear flushes the context */
+ flush = false;
/* Disable CMASK if flush_resource isn't going
* to be called.
*/
if (rtex->cmask.size)
- r600_texture_discard_cmask(rscreen, rtex);
+ si_texture_discard_cmask(sscreen, rtex);
}
/* Set metadata. */
if (!res->b.is_shared || update_metadata) {
- r600_texture_init_metadata(rscreen, rtex, &metadata);
- if (rscreen->query_opaque_metadata)
- rscreen->query_opaque_metadata(rscreen, rtex,
- &metadata);
+ r600_texture_init_metadata(sscreen, rtex, &metadata);
+ si_query_opaque_metadata(sscreen, rtex, &metadata);
- rscreen->ws->buffer_set_metadata(res->buf, &metadata);
+ sscreen->ws->buffer_set_metadata(res->buf, &metadata);
}
- if (rscreen->chip_class >= GFX9) {
+ if (sscreen->info.chip_class >= GFX9) {
offset = rtex->surface.u.gfx9.surf_offset;
stride = rtex->surface.u.gfx9.surf_pitch *
rtex->surface.bpe;
slice_size = (uint64_t)rtex->surface.u.legacy.level[0].slice_size_dw * 4;
}
} else {
+ /* Buffer exports are for the OpenCL interop. */
/* Move a suballocated buffer into a non-suballocated allocation. */
- if (rscreen->ws->buffer_is_suballocated(res->buf)) {
+ if (sscreen->ws->buffer_is_suballocated(res->buf) ||
+ /* A DMABUF export always fails if the BO is local. */
+ (rtex->resource.flags & RADEON_FLAG_NO_INTERPROCESS_SHARING &&
+ sscreen->info.has_local_buffers)) {
assert(!res->b.is_shared);
/* Allocate a new buffer with PIPE_BIND_SHARED. */
/* Copy the old buffer contents to the new one. */
struct pipe_box box;
u_box_1d(0, newb->width0, &box);
- rctx->b.resource_copy_region(&rctx->b, newb, 0, 0, 0, 0,
+ sctx->b.b.resource_copy_region(&sctx->b.b, newb, 0, 0, 0, 0,
&res->b.b, 0, &box);
+ flush = true;
/* Move the new buffer storage to the old pipe_resource. */
- si_replace_buffer_storage(&rctx->b, &res->b.b, newb);
+ si_replace_buffer_storage(&sctx->b.b, &res->b.b, newb);
pipe_resource_reference(&newb, NULL);
assert(res->b.b.bind & PIPE_BIND_SHARED);
slice_size = 0;
}
+ if (flush)
+ sctx->b.b.flush(&sctx->b.b, NULL, 0);
+
if (res->b.is_shared) {
/* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
* doesn't set it.
res->external_usage = usage;
}
- return rscreen->ws->buffer_get_handle(res->buf, stride, offset,
+ return sscreen->ws->buffer_get_handle(res->buf, stride, offset,
slice_size, whandle);
}
static const struct u_resource_vtbl r600_texture_vtbl;
/* The number of samples can be specified independently of the texture. */
-void si_texture_get_fmask_info(struct r600_common_screen *rscreen,
+void si_texture_get_fmask_info(struct si_screen *sscreen,
struct r600_texture *rtex,
unsigned nr_samples,
struct r600_fmask_info *out)
memset(out, 0, sizeof(*out));
- if (rscreen->chip_class >= GFX9) {
+ if (sscreen->info.chip_class >= GFX9) {
out->alignment = rtex->surface.u.gfx9.fmask_alignment;
out->size = rtex->surface.u.gfx9.fmask_size;
+ out->tile_swizzle = rtex->surface.u.gfx9.fmask_tile_swizzle;
return;
}
return;
}
- if (rscreen->ws->surface_init(rscreen->ws, &templ, flags, bpe,
+ if (sscreen->ws->surface_init(sscreen->ws, &templ, flags, bpe,
RADEON_SURF_MODE_2D, &fmask)) {
R600_ERR("Got error in surface_init while allocating FMASK.\n");
return;
out->size = fmask.surf_size;
}
-static void r600_texture_allocate_fmask(struct r600_common_screen *rscreen,
+static void r600_texture_allocate_fmask(struct si_screen *sscreen,
struct r600_texture *rtex)
{
- si_texture_get_fmask_info(rscreen, rtex,
+ si_texture_get_fmask_info(sscreen, rtex,
rtex->resource.b.b.nr_samples, &rtex->fmask);
rtex->fmask.offset = align64(rtex->size, rtex->fmask.alignment);
rtex->size = rtex->fmask.offset + rtex->fmask.size;
}
-void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
+void si_texture_get_cmask_info(struct si_screen *sscreen,
struct r600_texture *rtex,
struct r600_cmask_info *out)
{
- unsigned pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
- unsigned num_pipes = rscreen->info.num_tile_pipes;
+ unsigned pipe_interleave_bytes = sscreen->info.pipe_interleave_bytes;
+ unsigned num_pipes = sscreen->info.num_tile_pipes;
unsigned cl_width, cl_height;
- if (rscreen->chip_class >= GFX9) {
+ if (sscreen->info.chip_class >= GFX9) {
out->alignment = rtex->surface.u.gfx9.cmask_alignment;
out->size = rtex->surface.u.gfx9.cmask_size;
return;
out->slice_tile_max -= 1;
out->alignment = MAX2(256, base_align);
- out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
+ out->size = util_num_layers(&rtex->resource.b.b, 0) *
align(slice_bytes, base_align);
}
-static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen,
+static void r600_texture_allocate_cmask(struct si_screen *sscreen,
struct r600_texture *rtex)
{
- si_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
+ si_texture_get_cmask_info(sscreen, rtex, &rtex->cmask);
rtex->cmask.offset = align64(rtex->size, rtex->cmask.alignment);
rtex->size = rtex->cmask.offset + rtex->cmask.size;
rtex->cb_color_info |= S_028C70_FAST_CLEAR(1);
}
-static void r600_texture_get_htile_size(struct r600_common_screen *rscreen,
+static void r600_texture_get_htile_size(struct si_screen *sscreen,
struct r600_texture *rtex)
{
unsigned cl_width, cl_height, width, height;
unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
- unsigned num_pipes = rscreen->info.num_tile_pipes;
+ unsigned num_pipes = sscreen->info.num_tile_pipes;
- assert(rscreen->chip_class <= VI);
+ assert(sscreen->info.chip_class <= VI);
rtex->surface.htile_size = 0;
/* HTILE is broken with 1D tiling on old kernels and CIK. */
- if (rscreen->chip_class >= CIK &&
+ if (sscreen->info.chip_class >= CIK &&
rtex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_1D &&
- rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 38)
+ sscreen->info.drm_major == 2 && sscreen->info.drm_minor < 38)
return;
/* Overalign HTILE on P2 configs to work around GPU hangs in
* are always reproducible. I think I have seen the test hang
* on Carrizo too, though it was very rare there.
*/
- if (rscreen->chip_class >= CIK && num_pipes < 4)
+ if (sscreen->info.chip_class >= CIK && num_pipes < 4)
num_pipes = 4;
switch (num_pipes) {
slice_elements = (width * height) / (8 * 8);
slice_bytes = slice_elements * 4;
- pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
+ pipe_interleave_bytes = sscreen->info.pipe_interleave_bytes;
base_align = num_pipes * pipe_interleave_bytes;
rtex->surface.htile_alignment = base_align;
rtex->surface.htile_size =
- (util_max_layer(&rtex->resource.b.b, 0) + 1) *
+ util_num_layers(&rtex->resource.b.b, 0) *
align(slice_bytes, base_align);
}
-static void r600_texture_allocate_htile(struct r600_common_screen *rscreen,
+static void r600_texture_allocate_htile(struct si_screen *sscreen,
struct r600_texture *rtex)
{
- if (rscreen->chip_class <= VI && !rtex->tc_compatible_htile)
- r600_texture_get_htile_size(rscreen, rtex);
+ if (sscreen->info.chip_class <= VI && !rtex->tc_compatible_htile)
+ r600_texture_get_htile_size(sscreen, rtex);
if (!rtex->surface.htile_size)
return;
rtex->size = rtex->htile_offset + rtex->surface.htile_size;
}
-void si_print_texture_info(struct r600_common_screen *rscreen,
+void si_print_texture_info(struct si_screen *sscreen,
struct r600_texture *rtex, struct u_log_context *log)
{
int i;
rtex->surface.bpe, rtex->resource.b.b.nr_samples,
rtex->surface.flags, util_format_short_name(rtex->resource.b.b.format));
- if (rscreen->chip_class >= GFX9) {
+ if (sscreen->info.chip_class >= GFX9) {
u_log_printf(log, " Surf: size=%"PRIu64", slice_size=%"PRIu64", "
"alignment=%u, swmode=%u, epitch=%u, pitch=%u\n",
rtex->surface.surf_size,
{
struct r600_texture *rtex;
struct r600_resource *resource;
- struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
+ struct si_screen *sscreen = (struct si_screen*)screen;
rtex = CALLOC_STRUCT(r600_texture);
if (!rtex)
* - VI only supports Z32_FLOAT.
* - GFX9 only supports Z32_FLOAT and Z16_UNORM. */
if (rtex->tc_compatible_htile) {
- if (rscreen->chip_class >= GFX9 &&
+ if (sscreen->info.chip_class >= GFX9 &&
base->format == PIPE_FORMAT_Z16_UNORM)
rtex->db_render_format = base->format;
else {
rtex->ps_draw_ratio = 0;
if (rtex->is_depth) {
- if (rscreen->chip_class >= GFX9) {
+ if (sscreen->info.chip_class >= GFX9) {
rtex->can_sample_z = true;
rtex->can_sample_s = true;
} else {
R600_RESOURCE_FLAG_FLUSHED_DEPTH))) {
rtex->db_compatible = true;
- if (!(rscreen->debug_flags & DBG(NO_HYPERZ)))
- r600_texture_allocate_htile(rscreen, rtex);
+ if (!(sscreen->debug_flags & DBG(NO_HYPERZ)))
+ r600_texture_allocate_htile(sscreen, rtex);
}
} else {
- if (base->nr_samples > 1) {
- if (!buf) {
- r600_texture_allocate_fmask(rscreen, rtex);
- r600_texture_allocate_cmask(rscreen, rtex);
- rtex->cmask_buffer = &rtex->resource;
- }
+ if (base->nr_samples > 1 &&
+ !buf &&
+ !(sscreen->debug_flags & DBG(NO_FMASK))) {
+ r600_texture_allocate_fmask(sscreen, rtex);
+ r600_texture_allocate_cmask(sscreen, rtex);
+ rtex->cmask_buffer = &rtex->resource;
+
if (!rtex->fmask.size || !rtex->cmask.size) {
FREE(rtex);
return NULL;
* apply_opaque_metadata later.
*/
if (rtex->surface.dcc_size &&
- (buf || !(rscreen->debug_flags & DBG(NO_DCC))) &&
+ (buf || !(sscreen->debug_flags & DBG(NO_DCC))) &&
!(rtex->surface.flags & RADEON_SURF_SCANOUT)) {
/* Reserve space for the DCC buffer. */
rtex->dcc_offset = align64(rtex->size, rtex->surface.dcc_alignment);
/* Now create the backing buffer. */
if (!buf) {
- si_init_resource_fields(rscreen, resource, rtex->size,
+ si_init_resource_fields(sscreen, resource, rtex->size,
rtex->surface.surf_alignment);
- if (!si_alloc_resource(rscreen, resource)) {
+ if (!si_alloc_resource(sscreen, resource)) {
FREE(rtex);
return NULL;
}
} else {
resource->buf = buf;
- resource->gpu_address = rscreen->ws->buffer_get_virtual_address(resource->buf);
+ resource->gpu_address = sscreen->ws->buffer_get_virtual_address(resource->buf);
resource->bo_size = buf->size;
resource->bo_alignment = buf->alignment;
- resource->domains = rscreen->ws->buffer_get_initial_domain(resource->buf);
+ resource->domains = sscreen->ws->buffer_get_initial_domain(resource->buf);
if (resource->domains & RADEON_DOMAIN_VRAM)
resource->vram_usage = buf->size;
else if (resource->domains & RADEON_DOMAIN_GTT)
if (rtex->cmask.size) {
/* Initialize the cmask to 0xCC (= compressed state). */
- si_screen_clear_buffer(rscreen, &rtex->cmask_buffer->b.b,
+ si_screen_clear_buffer(sscreen, &rtex->cmask_buffer->b.b,
rtex->cmask.offset, rtex->cmask.size,
0xCCCCCCCC);
}
if (rtex->htile_offset) {
uint32_t clear_value = 0;
- if (rscreen->chip_class >= GFX9 || rtex->tc_compatible_htile)
+ if (sscreen->info.chip_class >= GFX9 || rtex->tc_compatible_htile)
clear_value = 0x0000030F;
- si_screen_clear_buffer(rscreen, &rtex->resource.b.b,
+ si_screen_clear_buffer(sscreen, &rtex->resource.b.b,
rtex->htile_offset,
rtex->surface.htile_size,
clear_value);
/* Initialize DCC only if the texture is not being imported. */
if (!buf && rtex->dcc_offset) {
- si_screen_clear_buffer(rscreen, &rtex->resource.b.b,
+ si_screen_clear_buffer(sscreen, &rtex->resource.b.b,
rtex->dcc_offset,
rtex->surface.dcc_size,
0xFFFFFFFF);
rtex->cmask.base_address_reg =
(rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
- if (rscreen->debug_flags & DBG(VM)) {
+ if (sscreen->debug_flags & DBG(VM)) {
fprintf(stderr, "VM start=0x%"PRIX64" end=0x%"PRIX64" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
rtex->resource.gpu_address,
rtex->resource.gpu_address + rtex->resource.buf->size,
- base->width0, base->height0, util_max_layer(base, 0)+1, base->last_level+1,
+ base->width0, base->height0, util_num_layers(base, 0), base->last_level+1,
base->nr_samples ? base->nr_samples : 1, util_format_short_name(base->format));
}
- if (rscreen->debug_flags & DBG(TEX)) {
+ if (sscreen->debug_flags & DBG(TEX)) {
puts("Texture:");
struct u_log_context log;
u_log_context_init(&log);
- si_print_texture_info(rscreen, rtex, &log);
+ si_print_texture_info(sscreen, rtex, &log);
u_log_new_page_print(&log, stdout);
fflush(stdout);
u_log_context_destroy(&log);
}
static enum radeon_surf_mode
-r600_choose_tiling(struct r600_common_screen *rscreen,
+r600_choose_tiling(struct si_screen *sscreen,
const struct pipe_resource *templ)
{
const struct util_format_description *desc = util_format_description(templ->format);
/* Avoid Z/S decompress blits by forcing TC-compatible HTILE on VI,
* which requires 2D tiling.
*/
- if (rscreen->chip_class == VI &&
+ if (sscreen->info.chip_class == VI &&
is_depth_stencil &&
(templ->flags & PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY))
return RADEON_SURF_MODE_2D;
if (!force_tiling &&
!is_depth_stencil &&
!util_format_is_compressed(templ->format)) {
- if (rscreen->debug_flags & DBG(NO_TILING))
+ if (sscreen->debug_flags & DBG(NO_TILING))
return RADEON_SURF_MODE_LINEAR_ALIGNED;
/* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
/* Make small textures 1D tiled. */
if (templ->width0 <= 16 || templ->height0 <= 16 ||
- (rscreen->debug_flags & DBG(NO_2D_TILING)))
+ (sscreen->debug_flags & DBG(NO_2D_TILING)))
return RADEON_SURF_MODE_1D;
/* The allocator will switch to 1D if needed. */
struct pipe_resource *si_texture_create(struct pipe_screen *screen,
const struct pipe_resource *templ)
{
- struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
+ struct si_screen *sscreen = (struct si_screen*)screen;
struct radeon_surf surface = {0};
bool is_flushed_depth = templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH;
bool tc_compatible_htile =
- rscreen->chip_class >= VI &&
+ sscreen->info.chip_class >= VI &&
(templ->flags & PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY) &&
- !(rscreen->debug_flags & DBG(NO_HYPERZ)) &&
+ !(sscreen->debug_flags & DBG(NO_HYPERZ)) &&
!is_flushed_depth &&
templ->nr_samples <= 1 && /* TC-compat HTILE is less efficient with MSAA */
util_format_is_depth_or_stencil(templ->format);
int r;
- r = r600_init_surface(rscreen, &surface, templ,
- r600_choose_tiling(rscreen, templ), 0, 0,
+ r = r600_init_surface(sscreen, &surface, templ,
+ r600_choose_tiling(sscreen, templ), 0, 0,
false, false, is_flushed_depth,
tc_compatible_htile);
if (r) {
struct winsys_handle *whandle,
unsigned usage)
{
- struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
+ struct si_screen *sscreen = (struct si_screen*)screen;
struct pb_buffer *buf = NULL;
unsigned stride = 0, offset = 0;
enum radeon_surf_mode array_mode;
templ->depth0 != 1 || templ->last_level != 0)
return NULL;
- buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride, &offset);
+ buf = sscreen->ws->buffer_from_handle(sscreen->ws, whandle, &stride, &offset);
if (!buf)
return NULL;
- rscreen->ws->buffer_get_metadata(buf, &metadata);
- r600_surface_import_metadata(rscreen, &surface, &metadata,
+ sscreen->ws->buffer_get_metadata(buf, &metadata);
+ r600_surface_import_metadata(sscreen, &surface, &metadata,
&array_mode, &is_scanout);
- r = r600_init_surface(rscreen, &surface, templ, array_mode, stride,
+ r = r600_init_surface(sscreen, &surface, templ, array_mode, stride,
offset, true, is_scanout, false, false);
if (r) {
return NULL;
rtex->resource.b.is_shared = true;
rtex->resource.external_usage = usage;
- if (rscreen->apply_opaque_metadata)
- rscreen->apply_opaque_metadata(rscreen, rtex, &metadata);
+ si_apply_opaque_metadata(sscreen, rtex, &metadata);
assert(rtex->surface.tile_swizzle == 0);
return &rtex->resource.b.b;
}
}
-static bool r600_can_invalidate_texture(struct r600_common_screen *rscreen,
+static bool r600_can_invalidate_texture(struct si_screen *sscreen,
struct r600_texture *rtex,
unsigned transfer_usage,
const struct pipe_box *box)
box->depth);
}
-static void r600_texture_invalidate_storage(struct r600_common_context *rctx,
+static void r600_texture_invalidate_storage(struct si_context *sctx,
struct r600_texture *rtex)
{
- struct r600_common_screen *rscreen = rctx->screen;
+ struct si_screen *sscreen = sctx->screen;
/* There is no point in discarding depth and tiled buffers. */
assert(!rtex->is_depth);
assert(rtex->surface.is_linear);
/* Reallocate the buffer in the same pipe_resource. */
- si_alloc_resource(rscreen, &rtex->resource);
+ si_alloc_resource(sscreen, &rtex->resource);
/* Initialize the CMASK base address (needed even without CMASK). */
rtex->cmask.base_address_reg =
(rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
- p_atomic_inc(&rscreen->dirty_tex_counter);
+ p_atomic_inc(&sscreen->dirty_tex_counter);
- rctx->num_alloc_tex_transfer_bytes += rtex->size;
+ sctx->b.num_alloc_tex_transfer_bytes += rtex->size;
}
static void *r600_texture_transfer_map(struct pipe_context *ctx,
const struct pipe_box *box,
struct pipe_transfer **ptransfer)
{
- struct r600_common_context *rctx = (struct r600_common_context*)ctx;
+ struct si_context *sctx = (struct si_context*)ctx;
struct r600_texture *rtex = (struct r600_texture*)texture;
struct r600_transfer *trans;
struct r600_resource *buf;
* On dGPUs, the staging texture is always faster.
* Only count uploads that are at least 4x4 pixels large.
*/
- if (!rctx->screen->info.has_dedicated_vram &&
+ if (!sctx->screen->info.has_dedicated_vram &&
level == 0 &&
box->width >= 4 && box->height >= 4 &&
p_atomic_inc_return(&rtex->num_level0_transfers) == 10) {
bool can_invalidate =
- r600_can_invalidate_texture(rctx->screen, rtex,
+ r600_can_invalidate_texture(sctx->screen, rtex,
usage, box);
- r600_reallocate_texture_inplace(rctx, rtex,
+ r600_reallocate_texture_inplace(sctx, rtex,
PIPE_BIND_LINEAR,
can_invalidate);
}
rtex->resource.domains & RADEON_DOMAIN_VRAM ||
rtex->resource.flags & RADEON_FLAG_GTT_WC;
/* Write & linear only: */
- else if (si_rings_is_buffer_referenced(rctx, rtex->resource.buf,
- RADEON_USAGE_READWRITE) ||
- !rctx->ws->buffer_wait(rtex->resource.buf, 0,
+ else if (si_rings_is_buffer_referenced(sctx, rtex->resource.buf,
+ RADEON_USAGE_READWRITE) ||
+ !sctx->b.ws->buffer_wait(rtex->resource.buf, 0,
RADEON_USAGE_READWRITE)) {
/* It's busy. */
- if (r600_can_invalidate_texture(rctx->screen, rtex,
+ if (r600_can_invalidate_texture(sctx->screen, rtex,
usage, box))
- r600_texture_invalidate_storage(rctx, rtex);
+ r600_texture_invalidate_storage(sctx, rtex);
else
use_staging_texture = true;
}
}
r600_copy_region_with_blit(ctx, temp, 0, 0, 0, 0, texture, level, box);
- rctx->blit_decompress_depth(ctx, (struct r600_texture*)temp, staging_depth,
- 0, 0, 0, box->depth, 0, 0);
+ si_blit_decompress_depth(ctx, (struct r600_texture*)temp, staging_depth,
+ 0, 0, 0, box->depth, 0, 0);
pipe_resource_reference(&temp, NULL);
}
/* Just get the strides. */
- r600_texture_get_offset(rctx->screen, staging_depth, level, NULL,
+ r600_texture_get_offset(sctx->screen, staging_depth, level, NULL,
&trans->b.b.stride,
&trans->b.b.layer_stride);
} else {
return NULL;
}
- rctx->blit_decompress_depth(ctx, rtex, staging_depth,
- level, level,
- box->z, box->z + box->depth - 1,
- 0, 0);
+ si_blit_decompress_depth(ctx, rtex, staging_depth,
+ level, level,
+ box->z, box->z + box->depth - 1,
+ 0, 0);
- offset = r600_texture_get_offset(rctx->screen, staging_depth,
+ offset = r600_texture_get_offset(sctx->screen, staging_depth,
level, box,
&trans->b.b.stride,
&trans->b.b.layer_stride);
trans->staging = &staging->resource;
/* Just get the strides. */
- r600_texture_get_offset(rctx->screen, staging, 0, NULL,
+ r600_texture_get_offset(sctx->screen, staging, 0, NULL,
&trans->b.b.stride,
&trans->b.b.layer_stride);
buf = trans->staging;
} else {
/* the resource is mapped directly */
- offset = r600_texture_get_offset(rctx->screen, rtex, level, box,
+ offset = r600_texture_get_offset(sctx->screen, rtex, level, box,
&trans->b.b.stride,
&trans->b.b.layer_stride);
buf = &rtex->resource;
}
- if (!(map = si_buffer_map_sync_with_rings(rctx, buf, usage))) {
+ if (!(map = si_buffer_map_sync_with_rings(sctx, buf, usage))) {
r600_resource_reference(&trans->staging, NULL);
FREE(trans);
return NULL;
static void r600_texture_transfer_unmap(struct pipe_context *ctx,
struct pipe_transfer* transfer)
{
- struct r600_common_context *rctx = (struct r600_common_context*)ctx;
+ struct si_context *sctx = (struct si_context*)ctx;
struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
struct pipe_resource *texture = transfer->resource;
struct r600_texture *rtex = (struct r600_texture*)texture;
}
if (rtransfer->staging) {
- rctx->num_alloc_tex_transfer_bytes += rtransfer->staging->buf->size;
+ sctx->b.num_alloc_tex_transfer_bytes += rtransfer->staging->buf->size;
r600_resource_reference(&rtransfer->staging, NULL);
}
*
* The result is that the kernel memory manager is never a bottleneck.
*/
- if (rctx->num_alloc_tex_transfer_bytes > rctx->screen->info.gart_size / 4) {
- rctx->gfx.flush(rctx, RADEON_FLUSH_ASYNC, NULL);
- rctx->num_alloc_tex_transfer_bytes = 0;
+ if (sctx->b.num_alloc_tex_transfer_bytes > sctx->screen->info.gart_size / 4) {
+ si_flush_gfx_cs(sctx, PIPE_FLUSH_ASYNC, NULL);
+ sctx->b.num_alloc_tex_transfer_bytes = 0;
}
pipe_resource_reference(&transfer->resource, NULL);
/* DCC channel type categories within which formats can be reinterpreted
* while keeping the same DCC encoding. The swizzle must also match. */
enum dcc_channel_type {
- dcc_channel_float32,
- dcc_channel_uint32,
- dcc_channel_sint32,
- dcc_channel_float16,
- dcc_channel_uint16,
- dcc_channel_sint16,
+ dcc_channel_float,
+ /* uint and sint can be merged if we never use TC-compatible DCC clear
+ * encoding with the clear value of 1. */
+ dcc_channel_uint,
+ dcc_channel_sint,
dcc_channel_uint_10_10_10_2,
- dcc_channel_uint8,
- dcc_channel_sint8,
dcc_channel_incompatible,
};
switch (desc->channel[i].size) {
case 32:
- if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT)
- return dcc_channel_float32;
- if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED)
- return dcc_channel_uint32;
- return dcc_channel_sint32;
case 16:
+ case 8:
if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT)
- return dcc_channel_float16;
+ return dcc_channel_float;
if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED)
- return dcc_channel_uint16;
- return dcc_channel_sint16;
+ return dcc_channel_uint;
+ return dcc_channel_sint;
case 10:
return dcc_channel_uint_10_10_10_2;
- case 8:
- if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED)
- return dcc_channel_uint8;
- return dcc_channel_sint8;
default:
return dcc_channel_incompatible;
}
/* This can't be merged with the above function, because
* vi_dcc_formats_compatible should be called only when DCC is enabled. */
-void vi_disable_dcc_if_incompatible_format(struct r600_common_context *rctx,
+void vi_disable_dcc_if_incompatible_format(struct si_context *sctx,
struct pipe_resource *tex,
unsigned level,
enum pipe_format view_format)
struct r600_texture *rtex = (struct r600_texture *)tex;
if (vi_dcc_formats_are_incompatible(tex, level, view_format))
- if (!si_texture_disable_dcc(rctx, (struct r600_texture*)tex))
- rctx->decompress_dcc(&rctx->b, rtex);
+ if (!si_texture_disable_dcc(sctx, (struct r600_texture*)tex))
+ si_decompress_dcc(&sctx->b.b, rtex);
}
struct pipe_surface *si_create_surface_custom(struct pipe_context *pipe,
/* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
-static void vi_dcc_clean_up_context_slot(struct r600_common_context *rctx,
+static void vi_dcc_clean_up_context_slot(struct si_context *sctx,
int slot)
{
int i;
- if (rctx->dcc_stats[slot].query_active)
- vi_separate_dcc_stop_query(&rctx->b,
- rctx->dcc_stats[slot].tex);
+ if (sctx->b.dcc_stats[slot].query_active)
+ vi_separate_dcc_stop_query(&sctx->b.b,
+ sctx->b.dcc_stats[slot].tex);
- for (i = 0; i < ARRAY_SIZE(rctx->dcc_stats[slot].ps_stats); i++)
- if (rctx->dcc_stats[slot].ps_stats[i]) {
- rctx->b.destroy_query(&rctx->b,
- rctx->dcc_stats[slot].ps_stats[i]);
- rctx->dcc_stats[slot].ps_stats[i] = NULL;
+ for (i = 0; i < ARRAY_SIZE(sctx->b.dcc_stats[slot].ps_stats); i++)
+ if (sctx->b.dcc_stats[slot].ps_stats[i]) {
+ sctx->b.b.destroy_query(&sctx->b.b,
+ sctx->b.dcc_stats[slot].ps_stats[i]);
+ sctx->b.dcc_stats[slot].ps_stats[i] = NULL;
}
- r600_texture_reference(&rctx->dcc_stats[slot].tex, NULL);
+ r600_texture_reference(&sctx->b.dcc_stats[slot].tex, NULL);
}
/**
* Return the per-context slot where DCC statistics queries for the texture live.
*/
-static unsigned vi_get_context_dcc_stats_index(struct r600_common_context *rctx,
+static unsigned vi_get_context_dcc_stats_index(struct si_context *sctx,
struct r600_texture *tex)
{
int i, empty_slot = -1;
/* Remove zombie textures (textures kept alive by this array only). */
- for (i = 0; i < ARRAY_SIZE(rctx->dcc_stats); i++)
- if (rctx->dcc_stats[i].tex &&
- rctx->dcc_stats[i].tex->resource.b.b.reference.count == 1)
- vi_dcc_clean_up_context_slot(rctx, i);
+ for (i = 0; i < ARRAY_SIZE(sctx->b.dcc_stats); i++)
+ if (sctx->b.dcc_stats[i].tex &&
+ sctx->b.dcc_stats[i].tex->resource.b.b.reference.count == 1)
+ vi_dcc_clean_up_context_slot(sctx, i);
/* Find the texture. */
- for (i = 0; i < ARRAY_SIZE(rctx->dcc_stats); i++) {
+ for (i = 0; i < ARRAY_SIZE(sctx->b.dcc_stats); i++) {
/* Return if found. */
- if (rctx->dcc_stats[i].tex == tex) {
- rctx->dcc_stats[i].last_use_timestamp = os_time_get();
+ if (sctx->b.dcc_stats[i].tex == tex) {
+ sctx->b.dcc_stats[i].last_use_timestamp = os_time_get();
return i;
}
/* Record the first seen empty slot. */
- if (empty_slot == -1 && !rctx->dcc_stats[i].tex)
+ if (empty_slot == -1 && !sctx->b.dcc_stats[i].tex)
empty_slot = i;
}
int oldest_slot = 0;
/* Find the oldest slot. */
- for (i = 1; i < ARRAY_SIZE(rctx->dcc_stats); i++)
- if (rctx->dcc_stats[oldest_slot].last_use_timestamp >
- rctx->dcc_stats[i].last_use_timestamp)
+ for (i = 1; i < ARRAY_SIZE(sctx->b.dcc_stats); i++)
+ if (sctx->b.dcc_stats[oldest_slot].last_use_timestamp >
+ sctx->b.dcc_stats[i].last_use_timestamp)
oldest_slot = i;
/* Clean up the oldest slot. */
- vi_dcc_clean_up_context_slot(rctx, oldest_slot);
+ vi_dcc_clean_up_context_slot(sctx, oldest_slot);
empty_slot = oldest_slot;
}
/* Add the texture to the new slot. */
- r600_texture_reference(&rctx->dcc_stats[empty_slot].tex, tex);
- rctx->dcc_stats[empty_slot].last_use_timestamp = os_time_get();
+ r600_texture_reference(&sctx->b.dcc_stats[empty_slot].tex, tex);
+ sctx->b.dcc_stats[empty_slot].last_use_timestamp = os_time_get();
return empty_slot;
}
void vi_separate_dcc_start_query(struct pipe_context *ctx,
struct r600_texture *tex)
{
- struct r600_common_context *rctx = (struct r600_common_context*)ctx;
- unsigned i = vi_get_context_dcc_stats_index(rctx, tex);
+ struct si_context *sctx = (struct si_context*)ctx;
+ unsigned i = vi_get_context_dcc_stats_index(sctx, tex);
- assert(!rctx->dcc_stats[i].query_active);
+ assert(!sctx->b.dcc_stats[i].query_active);
- if (!rctx->dcc_stats[i].ps_stats[0])
- rctx->dcc_stats[i].ps_stats[0] = vi_create_resuming_pipestats_query(ctx);
+ if (!sctx->b.dcc_stats[i].ps_stats[0])
+ sctx->b.dcc_stats[i].ps_stats[0] = vi_create_resuming_pipestats_query(ctx);
/* begin or resume the query */
- ctx->begin_query(ctx, rctx->dcc_stats[i].ps_stats[0]);
- rctx->dcc_stats[i].query_active = true;
+ ctx->begin_query(ctx, sctx->b.dcc_stats[i].ps_stats[0]);
+ sctx->b.dcc_stats[i].query_active = true;
}
/**
void vi_separate_dcc_stop_query(struct pipe_context *ctx,
struct r600_texture *tex)
{
- struct r600_common_context *rctx = (struct r600_common_context*)ctx;
- unsigned i = vi_get_context_dcc_stats_index(rctx, tex);
+ struct si_context *sctx = (struct si_context*)ctx;
+ unsigned i = vi_get_context_dcc_stats_index(sctx, tex);
- assert(rctx->dcc_stats[i].query_active);
- assert(rctx->dcc_stats[i].ps_stats[0]);
+ assert(sctx->b.dcc_stats[i].query_active);
+ assert(sctx->b.dcc_stats[i].ps_stats[0]);
/* pause or end the query */
- ctx->end_query(ctx, rctx->dcc_stats[i].ps_stats[0]);
- rctx->dcc_stats[i].query_active = false;
+ ctx->end_query(ctx, sctx->b.dcc_stats[i].ps_stats[0]);
+ sctx->b.dcc_stats[i].query_active = false;
}
static bool vi_should_enable_separate_dcc(struct r600_texture *tex)
}
/* Called by fast clear. */
-void vi_separate_dcc_try_enable(struct r600_common_context *rctx,
+void vi_separate_dcc_try_enable(struct si_context *sctx,
struct r600_texture *tex)
{
/* The intent is to use this with shared displayable back buffers,
/* Enable the DCC stat gathering. */
if (!tex->dcc_gather_statistics) {
tex->dcc_gather_statistics = true;
- vi_separate_dcc_start_query(&rctx->b, tex);
+ vi_separate_dcc_start_query(&sctx->b.b, tex);
}
if (!vi_should_enable_separate_dcc(tex))
assert(tex->surface.num_dcc_levels);
assert(!tex->dcc_separate_buffer);
- r600_texture_discard_cmask(rctx->screen, tex);
+ si_texture_discard_cmask(sctx->screen, tex);
/* Get a DCC buffer. */
if (tex->last_dcc_separate_buffer) {
tex->last_dcc_separate_buffer = NULL;
} else {
tex->dcc_separate_buffer = (struct r600_resource*)
- si_aligned_buffer_create(rctx->b.screen,
+ si_aligned_buffer_create(sctx->b.b.screen,
R600_RESOURCE_FLAG_UNMAPPABLE,
PIPE_USAGE_DEFAULT,
tex->surface.dcc_size,
void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
struct r600_texture *tex)
{
- struct r600_common_context *rctx = (struct r600_common_context*)ctx;
+ struct si_context *sctx = (struct si_context*)ctx;
struct pipe_query *tmp;
- unsigned i = vi_get_context_dcc_stats_index(rctx, tex);
- bool query_active = rctx->dcc_stats[i].query_active;
+ unsigned i = vi_get_context_dcc_stats_index(sctx, tex);
+ bool query_active = sctx->b.dcc_stats[i].query_active;
bool disable = false;
- if (rctx->dcc_stats[i].ps_stats[2]) {
+ if (sctx->b.dcc_stats[i].ps_stats[2]) {
union pipe_query_result result;
/* Read the results. */
- ctx->get_query_result(ctx, rctx->dcc_stats[i].ps_stats[2],
+ ctx->get_query_result(ctx, sctx->b.dcc_stats[i].ps_stats[2],
true, &result);
- si_query_hw_reset_buffers(rctx,
- (struct r600_query_hw*)
- rctx->dcc_stats[i].ps_stats[2]);
+ si_query_hw_reset_buffers(sctx,
+ (struct r600_query_hw*)
+ sctx->b.dcc_stats[i].ps_stats[2]);
/* Compute the approximate number of fullscreen draws. */
tex->ps_draw_ratio =
result.pipeline_statistics.ps_invocations /
(tex->resource.b.b.width0 * tex->resource.b.b.height0);
- rctx->last_tex_ps_draw_ratio = tex->ps_draw_ratio;
+ sctx->b.last_tex_ps_draw_ratio = tex->ps_draw_ratio;
disable = tex->dcc_separate_buffer &&
!vi_should_enable_separate_dcc(tex);
vi_separate_dcc_stop_query(ctx, tex);
/* Move the queries in the queue by one. */
- tmp = rctx->dcc_stats[i].ps_stats[2];
- rctx->dcc_stats[i].ps_stats[2] = rctx->dcc_stats[i].ps_stats[1];
- rctx->dcc_stats[i].ps_stats[1] = rctx->dcc_stats[i].ps_stats[0];
- rctx->dcc_stats[i].ps_stats[0] = tmp;
+ tmp = sctx->b.dcc_stats[i].ps_stats[2];
+ sctx->b.dcc_stats[i].ps_stats[2] = sctx->b.dcc_stats[i].ps_stats[1];
+ sctx->b.dcc_stats[i].ps_stats[1] = sctx->b.dcc_stats[i].ps_stats[0];
+ sctx->b.dcc_stats[i].ps_stats[0] = tmp;
/* create and start a new query as ps_stats[0] */
if (query_active)
struct winsys_handle *whandle,
bool dedicated)
{
- struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
+ struct si_screen *sscreen = (struct si_screen*)screen;
struct r600_memory_object *memobj = CALLOC_STRUCT(r600_memory_object);
struct pb_buffer *buf = NULL;
uint32_t stride, offset;
if (!memobj)
return NULL;
- buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle,
+ buf = sscreen->ws->buffer_from_handle(sscreen->ws, whandle,
&stride, &offset);
if (!buf) {
free(memobj);
uint64_t offset)
{
int r;
- struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
+ struct si_screen *sscreen = (struct si_screen*)screen;
struct r600_memory_object *memobj = (struct r600_memory_object *)_memobj;
struct r600_texture *rtex;
struct radeon_surf surface = {};
struct pb_buffer *buf = NULL;
if (memobj->b.dedicated) {
- rscreen->ws->buffer_get_metadata(memobj->buf, &metadata);
- r600_surface_import_metadata(rscreen, &surface, &metadata,
+ sscreen->ws->buffer_get_metadata(memobj->buf, &metadata);
+ r600_surface_import_metadata(sscreen, &surface, &metadata,
&array_mode, &is_scanout);
} else {
/**
}
- r = r600_init_surface(rscreen, &surface, templ,
+ r = r600_init_surface(sscreen, &surface, templ,
array_mode, memobj->stride,
offset, true, is_scanout,
false, false);
rtex->resource.b.is_shared = true;
rtex->resource.external_usage = PIPE_HANDLE_USAGE_READ_WRITE;
- if (rscreen->apply_opaque_metadata)
- rscreen->apply_opaque_metadata(rscreen, rtex, &metadata);
+ si_apply_opaque_metadata(sscreen, rtex, &metadata);
return &rtex->resource.b.b;
}
return true;
}
-void si_init_screen_texture_functions(struct r600_common_screen *rscreen)
+void si_init_screen_texture_functions(struct si_screen *sscreen)
{
- rscreen->b.resource_from_handle = r600_texture_from_handle;
- rscreen->b.resource_get_handle = r600_texture_get_handle;
- rscreen->b.resource_from_memobj = r600_texture_from_memobj;
- rscreen->b.memobj_create_from_handle = r600_memobj_from_handle;
- rscreen->b.memobj_destroy = r600_memobj_destroy;
- rscreen->b.check_resource_capability = si_check_resource_capability;
+ sscreen->b.resource_from_handle = r600_texture_from_handle;
+ sscreen->b.resource_get_handle = r600_texture_get_handle;
+ sscreen->b.resource_from_memobj = r600_texture_from_memobj;
+ sscreen->b.memobj_create_from_handle = r600_memobj_from_handle;
+ sscreen->b.memobj_destroy = r600_memobj_destroy;
+ sscreen->b.check_resource_capability = si_check_resource_capability;
}
-void si_init_context_texture_functions(struct r600_common_context *rctx)
+void si_init_context_texture_functions(struct si_context *sctx)
{
- rctx->b.create_surface = r600_create_surface;
- rctx->b.surface_destroy = r600_surface_destroy;
+ sctx->b.b.create_surface = r600_create_surface;
+ sctx->b.b.surface_destroy = r600_surface_destroy;
}
projects / mesa.git / blobdiff