gallium/radeon: add a function for adding llvm function attributes
[mesa.git] / src / gallium / drivers / radeon / r600_texture.c
index c787cfb78efae594ac2fd01d4b9a7560a94fd7e2..af206e43860d5181c1881ab9ab6d139639553cdd 100644 (file)
@@ -336,7 +336,7 @@ void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
                out->slice_tile_max -= 1;
 
        out->tile_mode_index = fmask.tiling_index[0];
-       out->pitch = fmask.level[0].nblk_x;
+       out->pitch_in_pixels = fmask.level[0].nblk_x;
        out->bank_height = fmask.bankh;
        out->alignment = MAX2(256, fmask.bo_alignment);
        out->size = fmask.bo_size;
@@ -361,8 +361,8 @@ void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
        unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height;
        unsigned element_bits = 4;
        unsigned cmask_cache_bits = 1024;
-       unsigned num_pipes = rscreen->tiling_info.num_channels;
-       unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
+       unsigned num_pipes = rscreen->info.num_tile_pipes;
+       unsigned pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
 
        unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
        unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;
@@ -380,6 +380,10 @@ void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
        assert(macro_tile_width % 128 == 0);
        assert(macro_tile_height % 128 == 0);
 
+       out->pitch = pitch_elements;
+       out->height = height;
+       out->xalign = macro_tile_width;
+       out->yalign = macro_tile_height;
        out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
        out->alignment = MAX2(256, base_align);
        out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
@@ -390,8 +394,8 @@ static void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
                                      struct r600_texture *rtex,
                                      struct r600_cmask_info *out)
 {
-       unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
-       unsigned num_pipes = rscreen->tiling_info.num_channels;
+       unsigned pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
+       unsigned num_pipes = rscreen->info.num_tile_pipes;
        unsigned cl_width, cl_height;
 
        switch (num_pipes) {
@@ -425,6 +429,10 @@ static void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
        /* Each element of CMASK is a nibble. */
        unsigned slice_bytes = slice_elements / 2;
 
+       out->pitch = width;
+       out->height = height;
+       out->xalign = cl_width * 8;
+       out->yalign = cl_height * 8;
        out->slice_tile_max = (width * height) / (128*128);
        if (out->slice_tile_max)
                out->slice_tile_max -= 1;
@@ -507,7 +515,7 @@ static unsigned r600_texture_get_htile_size(struct r600_common_screen *rscreen,
 {
        unsigned cl_width, cl_height, width, height;
        unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
-       unsigned num_pipes = rscreen->tiling_info.num_channels;
+       unsigned num_pipes = rscreen->info.num_tile_pipes;
 
        if (rscreen->chip_class <= EVERGREEN &&
            rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 26)
@@ -525,6 +533,10 @@ static unsigned r600_texture_get_htile_size(struct r600_common_screen *rscreen,
            rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 38)
                return 0;
 
+       /* Overalign HTILE on Stoney to fix piglit/depthstencil-render-miplevels 585. */
+       if (rscreen->family == CHIP_STONEY)
+               num_pipes = 4;
+
        switch (num_pipes) {
        case 1:
                cl_width = 32;
@@ -557,9 +569,14 @@ static unsigned r600_texture_get_htile_size(struct r600_common_screen *rscreen,
        slice_elements = (width * height) / (8 * 8);
        slice_bytes = slice_elements * 4;
 
-       pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
+       pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
        base_align = num_pipes * pipe_interleave_bytes;
 
+       rtex->htile.pitch = width;
+       rtex->htile.height = height;
+       rtex->htile.xalign = cl_width * 8;
+       rtex->htile.yalign = cl_height * 8;
+
        return (util_max_layer(&rtex->resource.b.b, 0) + 1) *
                align(slice_bytes, base_align);
 }
@@ -585,8 +602,7 @@ static void r600_texture_allocate_htile(struct r600_common_screen *rscreen,
        }
 }
 
-static void
-r600_print_texture_info(struct r600_texture *rtex, FILE *f)
+void r600_print_texture_info(struct r600_texture *rtex, FILE *f)
 {
        int i;
 
@@ -608,22 +624,25 @@ r600_print_texture_info(struct r600_texture *rtex, FILE *f)
                (rtex->surface.flags & RADEON_SURF_SCANOUT) != 0);
 
        if (rtex->fmask.size)
-               fprintf(f, "  FMask: offset=%u, size=%u, alignment=%u, pitch=%u, "
+               fprintf(f, "  FMask: offset=%u, size=%u, alignment=%u, pitch_in_pixels=%u, "
                        "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
                        rtex->fmask.offset, rtex->fmask.size, rtex->fmask.alignment,
-                       rtex->fmask.pitch, rtex->fmask.bank_height,
+                       rtex->fmask.pitch_in_pixels, rtex->fmask.bank_height,
                        rtex->fmask.slice_tile_max, rtex->fmask.tile_mode_index);
 
        if (rtex->cmask.size)
-               fprintf(f, "  CMask: offset=%u, size=%u, alignment=%u, "
-                       "slice_tile_max=%u\n",
+               fprintf(f, "  CMask: offset=%u, size=%u, alignment=%u, pitch=%u, "
+                       "height=%u, xalign=%u, yalign=%u, slice_tile_max=%u\n",
                        rtex->cmask.offset, rtex->cmask.size, rtex->cmask.alignment,
-                       rtex->cmask.slice_tile_max);
+                       rtex->cmask.pitch, rtex->cmask.height, rtex->cmask.xalign,
+                       rtex->cmask.yalign, rtex->cmask.slice_tile_max);
 
        if (rtex->htile_buffer)
-               fprintf(f, "  HTile: size=%u, alignment=%u\n",
+               fprintf(f, "  HTile: size=%u, alignment=%u, pitch=%u, height=%u, "
+                       "xalign=%u, yalign=%u\n",
                        rtex->htile_buffer->b.b.width0,
-                       rtex->htile_buffer->buf->alignment);
+                       rtex->htile_buffer->buf->alignment, rtex->htile.pitch,
+                       rtex->htile.height, rtex->htile.xalign, rtex->htile.yalign);
 
        if (rtex->dcc_buffer) {
                fprintf(f, "  DCC: size=%u, alignment=%u\n",
@@ -684,7 +703,7 @@ r600_texture_create_object(struct pipe_screen *screen,
        struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 
        rtex = CALLOC_STRUCT(r600_texture);
-       if (rtex == NULL)
+       if (!rtex)
                return NULL;
 
        resource = &rtex->resource;
@@ -739,9 +758,8 @@ r600_texture_create_object(struct pipe_screen *screen,
                }
        } else {
                resource->buf = buf;
-               resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf);
-               resource->gpu_address = rscreen->ws->buffer_get_virtual_address(resource->cs_buf);
-               resource->domains = rscreen->ws->buffer_get_initial_domain(resource->cs_buf);
+               resource->gpu_address = rscreen->ws->buffer_get_virtual_address(resource->buf);
+               resource->domains = rscreen->ws->buffer_get_initial_domain(resource->buf);
        }
 
        if (rtex->cmask.size) {
@@ -1009,7 +1027,7 @@ static void *r600_texture_transfer_map(struct pipe_context *ctx,
                /* Untiled buffers in VRAM, which is slow for CPU reads */
                use_staging_texture = TRUE;
        } else if (!(usage & PIPE_TRANSFER_READ) &&
-           (r600_rings_is_buffer_referenced(rctx, rtex->resource.cs_buf, RADEON_USAGE_READWRITE) ||
+           (r600_rings_is_buffer_referenced(rctx, rtex->resource.buf, RADEON_USAGE_READWRITE) ||
             !rctx->ws->buffer_wait(rtex->resource.buf, 0, RADEON_USAGE_READWRITE))) {
                /* Use a staging texture for uploads if the underlying BO is busy. */
                use_staging_texture = TRUE;
@@ -1024,7 +1042,7 @@ static void *r600_texture_transfer_map(struct pipe_context *ctx,
        }
 
        trans = CALLOC_STRUCT(r600_transfer);
-       if (trans == NULL)
+       if (!trans)
                return NULL;
        trans->transfer.resource = texture;
        trans->transfer.level = level;
@@ -1066,7 +1084,7 @@ static void *r600_texture_transfer_map(struct pipe_context *ctx,
                                r600_copy_region_with_blit(ctx, temp, 0, 0, 0, 0, texture, level, box);
                                rctx->blit_decompress_depth(ctx, (struct r600_texture*)temp, staging_depth,
                                                            0, 0, 0, box->depth, 0, 0);
-                               pipe_resource_reference((struct pipe_resource**)&temp, NULL);
+                               pipe_resource_reference(&temp, NULL);
                        }
                }
                else {
@@ -1100,7 +1118,7 @@ static void *r600_texture_transfer_map(struct pipe_context *ctx,
 
                /* Create the temporary texture. */
                staging = (struct r600_texture*)ctx->screen->resource_create(ctx->screen, &resource);
-               if (staging == NULL) {
+               if (!staging) {
                        R600_ERR("failed to create temporary texture to hold untiled copy\n");
                        FREE(trans);
                        return NULL;
@@ -1177,7 +1195,7 @@ struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
 {
        struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
 
-       if (surface == NULL)
+       if (!surface)
                return NULL;
 
        assert(templ->u.tex.first_layer <= util_max_layer(texture, templ->u.tex.level));
@@ -1198,10 +1216,30 @@ static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
                                                const struct pipe_surface *templ)
 {
        unsigned level = templ->u.tex.level;
+       unsigned width = u_minify(tex->width0, level);
+       unsigned height = u_minify(tex->height0, level);
+
+       if (tex->target != PIPE_BUFFER && templ->format != tex->format) {
+               const struct util_format_description *tex_desc
+                       = util_format_description(tex->format);
+               const struct util_format_description *templ_desc
+                       = util_format_description(templ->format);
+
+               assert(tex_desc->block.bits == templ_desc->block.bits);
+
+               /* Adjust size of surface if and only if the block width or
+                * height is changed. */
+               if (tex_desc->block.width != templ_desc->block.width ||
+                   tex_desc->block.height != templ_desc->block.height) {
+                       unsigned nblks_x = util_format_get_nblocksx(tex->format, width);
+                       unsigned nblks_y = util_format_get_nblocksy(tex->format, height);
+
+                       width = nblks_x * templ_desc->block.width;
+                       height = nblks_y * templ_desc->block.height;
+               }
+       }
 
-       return r600_create_surface_custom(pipe, tex, templ,
-                                         u_minify(tex->width0, level),
-                                         u_minify(tex->height0, level));
+       return r600_create_surface_custom(pipe, tex, templ, width, height);
 }
 
 static void r600_surface_destroy(struct pipe_context *pipe,
@@ -1430,6 +1468,10 @@ void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
                        if (clear_words_needed)
                                tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
                } else {
+                       /* Stoney/RB+ doesn't work with CMASK fast clear. */
+                       if (rctx->family == CHIP_STONEY)
+                               continue;
+
                        /* ensure CMASK is enabled */
                        r600_texture_alloc_cmask_separate(rctx->screen, tex);
                        if (tex->cmask.size == 0) {