*/
#include "radeonsi/si_pipe.h"
-#include "r600_cs.h"
#include "r600_query.h"
#include "util/u_format.h"
#include "util/u_log.h"
}
if (sscreen->info.chip_class >= VI &&
- (ptex->flags & R600_RESOURCE_FLAG_DISABLE_DCC ||
+ (ptex->flags & SI_RESOURCE_FLAG_DISABLE_DCC ||
ptex->format == PIPE_FORMAT_R9G9B9E5_FLOAT ||
/* DCC MSAA array textures are disallowed due to incomplete clear impl. */
(ptex->nr_samples >= 2 &&
flags |= RADEON_SURF_SHAREABLE;
if (is_imported)
flags |= RADEON_SURF_IMPORTED | RADEON_SURF_SHAREABLE;
- if (!(ptex->flags & R600_RESOURCE_FLAG_FORCE_TILING))
+ if (!(ptex->flags & SI_RESOURCE_FLAG_FORCE_TILING))
flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
r = sscreen->ws->surface_init(sscreen->ws, ptex, flags, bpe,
bpe = 4;
break;
default:
- R600_ERR("Invalid sample count for FMASK allocation.\n");
+ PRINT_ERR("Invalid sample count for FMASK allocation.\n");
return;
}
if (sscreen->ws->surface_init(sscreen->ws, &templ, flags, bpe,
RADEON_SURF_MODE_2D, &fmask)) {
- R600_ERR("Got error in surface_init while allocating FMASK.\n");
+ PRINT_ERR("Got error in surface_init while allocating FMASK.\n");
return;
}
rtex->can_sample_s = !rtex->surface.u.legacy.stencil_adjusted;
}
- if (!(base->flags & (R600_RESOURCE_FLAG_TRANSFER |
- R600_RESOURCE_FLAG_FLUSHED_DEPTH))) {
+ if (!(base->flags & (SI_RESOURCE_FLAG_TRANSFER |
+ SI_RESOURCE_FLAG_FLUSHED_DEPTH))) {
rtex->db_compatible = true;
if (!(sscreen->debug_flags & DBG(NO_HYPERZ)))
const struct pipe_resource *templ)
{
const struct util_format_description *desc = util_format_description(templ->format);
- bool force_tiling = templ->flags & R600_RESOURCE_FLAG_FORCE_TILING;
+ bool force_tiling = templ->flags & SI_RESOURCE_FLAG_FORCE_TILING;
bool is_depth_stencil = util_format_is_depth_or_stencil(templ->format) &&
- !(templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
+ !(templ->flags & SI_RESOURCE_FLAG_FLUSHED_DEPTH);
/* MSAA resources must be 2D tiled. */
if (templ->nr_samples > 1)
return RADEON_SURF_MODE_2D;
/* Transfer resources should be linear. */
- if (templ->flags & R600_RESOURCE_FLAG_TRANSFER)
+ if (templ->flags & SI_RESOURCE_FLAG_TRANSFER)
return RADEON_SURF_MODE_LINEAR_ALIGNED;
/* Avoid Z/S decompress blits by forcing TC-compatible HTILE on VI,
{
struct si_screen *sscreen = (struct si_screen*)screen;
struct radeon_surf surface = {0};
- bool is_flushed_depth = templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH;
+ bool is_flushed_depth = templ->flags & SI_RESOURCE_FLAG_FLUSHED_DEPTH;
bool tc_compatible_htile =
sscreen->info.chip_class >= VI &&
(templ->flags & PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY) &&
resource.nr_samples = texture->nr_samples;
resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
- resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
+ resource.flags = texture->flags | SI_RESOURCE_FLAG_FLUSHED_DEPTH;
if (staging)
- resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
+ resource.flags |= SI_RESOURCE_FLAG_TRANSFER;
*flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
if (*flushed_depth_texture == NULL) {
- R600_ERR("failed to create temporary texture to hold flushed depth\n");
+ PRINT_ERR("failed to create temporary texture to hold flushed depth\n");
return false;
}
return true;
res->height0 = box->height;
res->depth0 = 1;
res->array_size = 1;
- res->usage = flags & R600_RESOURCE_FLAG_TRANSFER ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
+ res->usage = flags & SI_RESOURCE_FLAG_TRANSFER ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
res->flags = flags;
/* We must set the correct texture target and dimensions for a 3D box. */
char *map;
bool use_staging_texture = false;
- assert(!(texture->flags & R600_RESOURCE_FLAG_TRANSFER));
+ assert(!(texture->flags & SI_RESOURCE_FLAG_TRANSFER));
assert(box->width && box->height && box->depth);
/* Depth textures use staging unconditionally. */
si_init_temp_resource_from_box(&resource, texture, box, level, 0);
if (!si_init_flushed_depth_texture(ctx, &resource, &staging_depth)) {
- R600_ERR("failed to create temporary texture to hold untiled copy\n");
+ PRINT_ERR("failed to create temporary texture to hold untiled copy\n");
FREE(trans);
return NULL;
}
if (usage & PIPE_TRANSFER_READ) {
struct pipe_resource *temp = ctx->screen->resource_create(ctx->screen, &resource);
if (!temp) {
- R600_ERR("failed to create a temporary depth texture\n");
+ PRINT_ERR("failed to create a temporary depth texture\n");
FREE(trans);
return NULL;
}
/* XXX: only readback the rectangle which is being mapped? */
/* XXX: when discard is true, no need to read back from depth texture */
if (!si_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
- R600_ERR("failed to create temporary texture to hold untiled copy\n");
+ PRINT_ERR("failed to create temporary texture to hold untiled copy\n");
FREE(trans);
return NULL;
}
struct r600_texture *staging;
si_init_temp_resource_from_box(&resource, texture, box, level,
- R600_RESOURCE_FLAG_TRANSFER);
+ SI_RESOURCE_FLAG_TRANSFER);
resource.usage = (usage & PIPE_TRANSFER_READ) ?
PIPE_USAGE_STAGING : PIPE_USAGE_STREAM;
/* Create the temporary texture. */
staging = (struct r600_texture*)ctx->screen->resource_create(ctx->screen, &resource);
if (!staging) {
- R600_ERR("failed to create temporary texture to hold untiled copy\n");
+ PRINT_ERR("failed to create temporary texture to hold untiled copy\n");
FREE(trans);
return NULL;
}
struct si_query_hw *query = (struct si_query_hw*)
sctx->b.b.create_query(&sctx->b.b, PIPE_QUERY_PIPELINE_STATISTICS, 0);
- query->flags |= R600_QUERY_HW_FLAG_BEGIN_RESUMES;
+ query->flags |= SI_QUERY_HW_FLAG_BEGIN_RESUMES;
return (struct pipe_query*)query;
}
} else {
tex->dcc_separate_buffer = (struct r600_resource*)
si_aligned_buffer_create(sctx->b.b.screen,
- R600_RESOURCE_FLAG_UNMAPPABLE,
+ SI_RESOURCE_FLAG_UNMAPPABLE,
PIPE_USAGE_DEFAULT,
tex->surface.dcc_size,
tex->surface.dcc_alignment);
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