if (!rctx->dma.cs)
return false;
- if (util_format_get_blocksizebits(rdst->resource.b.b.format) !=
- util_format_get_blocksizebits(rsrc->resource.b.b.format))
+ if (rdst->surface.bpe != rsrc->surface.bpe)
return false;
/* MSAA: Blits don't exist in the real world. */
* src: Use the 3D path. DCC decompression is expensive.
* dst: Use the 3D path to compress the pixels with DCC.
*/
- if ((rsrc->dcc_offset && rsrc->surface.level[src_level].dcc_enabled) ||
- (rdst->dcc_offset && rdst->surface.level[dst_level].dcc_enabled))
+ if ((rsrc->dcc_offset && src_level < rsrc->surface.num_dcc_levels) ||
+ (rdst->dcc_offset && dst_level < rdst->surface.num_dcc_levels))
return false;
/* CMASK as:
static unsigned r600_texture_get_offset(struct r600_texture *rtex, unsigned level,
const struct pipe_box *box)
{
- enum pipe_format format = rtex->resource.b.b.format;
-
return rtex->surface.level[level].offset +
box->z * rtex->surface.level[level].slice_size +
- box->y / util_format_get_blockheight(format) * rtex->surface.level[level].pitch_bytes +
- box->x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
+ (box->y / rtex->surface.blk_h *
+ rtex->surface.level[level].nblk_x +
+ box->x / rtex->surface.blk_w) * rtex->surface.bpe;
}
static int r600_init_surface(struct r600_common_screen *rscreen,
flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
}
- if (is_stencil) {
- flags |= RADEON_SURF_SBUFFER |
- RADEON_SURF_HAS_SBUFFER_MIPTREE;
- }
- }
-
- if (rscreen->chip_class >= SI) {
- flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
+ if (is_stencil)
+ flags |= RADEON_SURF_SBUFFER;
}
if (rscreen->chip_class >= VI &&
if (is_imported)
flags |= RADEON_SURF_IMPORTED;
+ if (!(ptex->flags & R600_RESOURCE_FLAG_FORCE_TILING))
+ flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
r = rscreen->ws->surface_init(rscreen->ws, ptex, flags, bpe,
array_mode, surface);
return r;
}
- if (pitch_in_bytes_override && pitch_in_bytes_override != surface->level[0].pitch_bytes) {
+ if (pitch_in_bytes_override &&
+ pitch_in_bytes_override != surface->level[0].nblk_x * bpe) {
/* old ddx on evergreen over estimate alignment for 1d, only 1 level
* for those
*/
surface->level[0].nblk_x = pitch_in_bytes_override / bpe;
- surface->level[0].pitch_bytes = pitch_in_bytes_override;
surface->level[0].slice_size = pitch_in_bytes_override * surface->level[0].nblk_y;
}
metadata->tile_split = surface->tile_split;
metadata->mtilea = surface->mtilea;
metadata->num_banks = surface->num_banks;
- metadata->stride = surface->level[0].pitch_bytes;
+ metadata->stride = surface->level[0].nblk_x * surface->bpe;
metadata->scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
}
-static void r600_dirty_all_framebuffer_states(struct r600_common_screen *rscreen)
-{
- p_atomic_inc(&rscreen->dirty_fb_counter);
-}
-
static void r600_eliminate_fast_color_clear(struct r600_common_context *rctx,
struct r600_texture *rtex)
{
struct pipe_context *ctx = &rctx->b;
if (ctx == rscreen->aux_context)
- pipe_mutex_lock(rscreen->aux_context_lock);
+ mtx_lock(&rscreen->aux_context_lock);
ctx->flush_resource(ctx, &rtex->resource.b.b);
ctx->flush(ctx, NULL, 0);
if (ctx == rscreen->aux_context)
- pipe_mutex_unlock(rscreen->aux_context_lock);
+ mtx_unlock(&rscreen->aux_context_lock);
}
static void r600_texture_discard_cmask(struct r600_common_screen *rscreen,
r600_resource_reference(&rtex->cmask_buffer, NULL);
/* Notify all contexts about the change. */
- r600_dirty_all_framebuffer_states(rscreen);
+ p_atomic_inc(&rscreen->dirty_tex_counter);
p_atomic_inc(&rscreen->compressed_colortex_counter);
}
rtex->dcc_offset = 0;
/* Notify all contexts about the change. */
- r600_dirty_all_framebuffer_states(rscreen);
+ p_atomic_inc(&rscreen->dirty_tex_counter);
return true;
}
return false;
if (&rctx->b == rscreen->aux_context)
- pipe_mutex_lock(rscreen->aux_context_lock);
+ mtx_lock(&rscreen->aux_context_lock);
/* Decompress DCC. */
rctx->decompress_dcc(&rctx->b, rtex);
rctx->b.flush(&rctx->b, NULL, 0);
if (&rctx->b == rscreen->aux_context)
- pipe_mutex_unlock(rscreen->aux_context_lock);
+ mtx_unlock(&rscreen->aux_context_lock);
return r600_texture_discard_dcc(rscreen, rtex);
}
return;
if (rtex->resource.is_shared ||
- rtex->surface.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED)
+ rtex->surface.is_linear)
return;
/* This fails with MSAA, depth, and compressed textures. */
r600_texture_reference(&new_tex, NULL);
- r600_dirty_all_framebuffer_states(rctx->screen);
- p_atomic_inc(&rctx->screen->dirty_tex_descriptor_counter);
+ p_atomic_inc(&rctx->screen->dirty_tex_counter);
}
static boolean r600_texture_get_handle(struct pipe_screen* screen,
}
return rscreen->ws->buffer_get_handle(res->buf,
- rtex->surface.level[0].pitch_bytes,
+ rtex->surface.level[0].nblk_x *
+ rtex->surface.bpe,
rtex->surface.level[0].offset,
rtex->surface.level[0].slice_size,
whandle);
templ.nr_samples = 1;
flags = rtex->surface.flags | RADEON_SURF_FMASK;
- /* Use the same parameters and tile mode. */
- fmask.bankw = rtex->surface.bankw;
- fmask.bankh = rtex->surface.bankh;
- fmask.mtilea = rtex->surface.mtilea;
- fmask.tile_split = rtex->surface.tile_split;
+ if (rscreen->chip_class <= CAYMAN) {
+ /* Use the same parameters and tile mode. */
+ fmask.bankw = rtex->surface.bankw;
+ fmask.bankh = rtex->surface.bankh;
+ fmask.mtilea = rtex->surface.mtilea;
+ fmask.tile_split = rtex->surface.tile_split;
- if (rscreen->chip_class >= SI) {
- flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
+ if (nr_samples <= 4)
+ fmask.bankh = 4;
}
switch (nr_samples) {
case 2:
case 4:
bpe = 1;
- if (rscreen->chip_class <= CAYMAN) {
- fmask.bankh = 4;
- }
break;
case 8:
bpe = 4;
out->tile_mode_index = fmask.tiling_index[0];
out->pitch_in_pixels = fmask.level[0].nblk_x;
out->bank_height = fmask.bankh;
- out->alignment = MAX2(256, fmask.bo_alignment);
- out->size = fmask.bo_size;
+ out->alignment = MAX2(256, fmask.surf_alignment);
+ out->size = fmask.surf_size;
}
static void r600_texture_allocate_fmask(struct r600_common_screen *rscreen,
assert(macro_tile_width % 128 == 0);
assert(macro_tile_height % 128 == 0);
- out->pitch = pitch_elements;
- out->height = height;
- out->xalign = macro_tile_width;
- out->yalign = macro_tile_height;
out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
out->alignment = MAX2(256, base_align);
out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
/* Each element of CMASK is a nibble. */
unsigned slice_bytes = slice_elements / 2;
- out->pitch = width;
- out->height = height;
- out->xalign = cl_width * 8;
- out->yalign = cl_height * 8;
out->slice_tile_max = (width * height) / (128*128);
if (out->slice_tile_max)
out->slice_tile_max -= 1;
}
rtex->cmask_buffer = (struct r600_resource *)
- r600_aligned_buffer_create(&rscreen->b, 0, PIPE_USAGE_DEFAULT,
+ r600_aligned_buffer_create(&rscreen->b,
+ R600_RESOURCE_FLAG_UNMAPPABLE,
+ PIPE_USAGE_DEFAULT,
rtex->cmask.size,
rtex->cmask.alignment);
if (rtex->cmask_buffer == NULL) {
p_atomic_inc(&rscreen->compressed_colortex_counter);
}
-static unsigned r600_texture_get_htile_size(struct r600_common_screen *rscreen,
- struct r600_texture *rtex)
+static void r600_texture_get_htile_size(struct r600_common_screen *rscreen,
+ struct r600_texture *rtex)
{
unsigned cl_width, cl_height, width, height;
unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
unsigned num_pipes = rscreen->info.num_tile_pipes;
+ rtex->surface.htile_size = 0;
+
if (rscreen->chip_class <= EVERGREEN &&
rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 26)
- return 0;
+ return;
/* HW bug on R6xx. */
if (rscreen->chip_class == R600 &&
(rtex->resource.b.b.width0 > 7680 ||
rtex->resource.b.b.height0 > 7680))
- return 0;
+ return;
/* HTILE is broken with 1D tiling on old kernels and CIK. */
if (rscreen->chip_class >= CIK &&
rtex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 38)
- return 0;
+ return;
/* Overalign HTILE on P2 configs to work around GPU hangs in
* piglit/depthstencil-render-miplevels 585.
break;
default:
assert(0);
- return 0;
+ return;
}
width = align(rtex->resource.b.b.width0, cl_width * 8);
pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
base_align = num_pipes * pipe_interleave_bytes;
- rtex->htile.pitch = width;
- rtex->htile.height = height;
- rtex->htile.xalign = cl_width * 8;
- rtex->htile.yalign = cl_height * 8;
- rtex->htile.alignment = base_align;
-
- return (util_max_layer(&rtex->resource.b.b, 0) + 1) *
+ rtex->surface.htile_alignment = base_align;
+ rtex->surface.htile_size =
+ (util_max_layer(&rtex->resource.b.b, 0) + 1) *
align(slice_bytes, base_align);
}
static void r600_texture_allocate_htile(struct r600_common_screen *rscreen,
struct r600_texture *rtex)
{
- uint64_t htile_size, alignment;
uint32_t clear_value;
if (rtex->tc_compatible_htile) {
- htile_size = rtex->surface.htile_size;
- alignment = rtex->surface.htile_alignment;
clear_value = 0x0000030F;
} else {
- htile_size = r600_texture_get_htile_size(rscreen, rtex);
- alignment = rtex->htile.alignment;
+ r600_texture_get_htile_size(rscreen, rtex);
clear_value = 0;
}
- if (!htile_size)
+ if (!rtex->surface.htile_size)
return;
rtex->htile_buffer = (struct r600_resource*)
- r600_aligned_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
- PIPE_USAGE_DEFAULT,
- htile_size, alignment);
+ r600_aligned_buffer_create(&rscreen->b,
+ R600_RESOURCE_FLAG_UNMAPPABLE,
+ PIPE_USAGE_DEFAULT,
+ rtex->surface.htile_size,
+ rtex->surface.htile_alignment);
if (rtex->htile_buffer == NULL) {
/* this is not a fatal error as we can still keep rendering
* without htile buffer */
R600_ERR("Failed to create buffer object for htile buffer.\n");
} else {
r600_screen_clear_buffer(rscreen, &rtex->htile_buffer->b.b,
- 0, htile_size, clear_value,
- R600_COHERENCY_NONE);
+ 0, rtex->surface.htile_size,
+ clear_value);
}
}
fprintf(f, " Layout: size=%"PRIu64", alignment=%u, bankw=%u, "
"bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
- rtex->surface.bo_size, rtex->surface.bo_alignment, rtex->surface.bankw,
+ rtex->surface.surf_size, rtex->surface.surf_alignment, rtex->surface.bankw,
rtex->surface.bankh, rtex->surface.num_banks, rtex->surface.mtilea,
rtex->surface.tile_split, rtex->surface.pipe_config,
(rtex->surface.flags & RADEON_SURF_SCANOUT) != 0);
rtex->fmask.slice_tile_max, rtex->fmask.tile_mode_index);
if (rtex->cmask.size)
- fprintf(f, " CMask: offset=%"PRIu64", size=%"PRIu64", alignment=%u, pitch=%u, "
- "height=%u, xalign=%u, yalign=%u, slice_tile_max=%u\n",
+ fprintf(f, " CMask: offset=%"PRIu64", size=%"PRIu64", alignment=%u, "
+ "slice_tile_max=%u\n",
rtex->cmask.offset, rtex->cmask.size, rtex->cmask.alignment,
- rtex->cmask.pitch, rtex->cmask.height, rtex->cmask.xalign,
- rtex->cmask.yalign, rtex->cmask.slice_tile_max);
+ rtex->cmask.slice_tile_max);
if (rtex->htile_buffer)
- fprintf(f, " HTile: size=%u, alignment=%u, pitch=%u, height=%u, "
- "xalign=%u, yalign=%u, TC_compatible = %u\n",
+ fprintf(f, " HTile: size=%u, alignment=%u, TC_compatible = %u\n",
rtex->htile_buffer->b.b.width0,
- rtex->htile_buffer->buf->alignment, rtex->htile.pitch,
- rtex->htile.height, rtex->htile.xalign, rtex->htile.yalign,
+ rtex->htile_buffer->buf->alignment,
rtex->tc_compatible_htile);
if (rtex->dcc_offset) {
for (i = 0; i <= rtex->resource.b.b.last_level; i++)
fprintf(f, " DCCLevel[%i]: enabled=%u, offset=%"PRIu64", "
"fast_clear_size=%"PRIu64"\n",
- i, rtex->surface.level[i].dcc_enabled,
+ i, i < rtex->surface.num_dcc_levels,
rtex->surface.level[i].dcc_offset,
rtex->surface.level[i].dcc_fast_clear_size);
}
for (i = 0; i <= rtex->resource.b.b.last_level; i++)
fprintf(f, " Level[%i]: offset=%"PRIu64", slice_size=%"PRIu64", "
"npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
- "pitch_bytes=%u, mode=%u\n",
+ "mode=%u, tiling_index = %u\n",
i, rtex->surface.level[i].offset,
rtex->surface.level[i].slice_size,
u_minify(rtex->resource.b.b.width0, i),
u_minify(rtex->resource.b.b.depth0, i),
rtex->surface.level[i].nblk_x,
rtex->surface.level[i].nblk_y,
- rtex->surface.level[i].pitch_bytes,
- rtex->surface.level[i].mode);
+ rtex->surface.level[i].mode,
+ rtex->surface.tiling_index[i]);
if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
fprintf(f, " StencilLayout: tilesplit=%u\n",
fprintf(f, " StencilLevel[%i]: offset=%"PRIu64", "
"slice_size=%"PRIu64", npix_x=%u, "
"npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
- "pitch_bytes=%u, mode=%u\n",
+ "mode=%u, tiling_index = %u\n",
i, rtex->surface.stencil_level[i].offset,
rtex->surface.stencil_level[i].slice_size,
u_minify(rtex->resource.b.b.width0, i),
u_minify(rtex->resource.b.b.depth0, i),
rtex->surface.stencil_level[i].nblk_x,
rtex->surface.stencil_level[i].nblk_y,
- rtex->surface.stencil_level[i].pitch_bytes,
- rtex->surface.stencil_level[i].mode);
+ rtex->surface.stencil_level[i].mode,
+ rtex->surface.stencil_tiling_index[i]);
}
}
}
rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
rtex->surface = *surface;
- rtex->size = rtex->surface.bo_size;
+ rtex->size = rtex->surface.surf_size;
- rtex->tc_compatible_htile = rtex->surface.htile_size != 0;
- assert(!!(rtex->surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE) ==
- rtex->tc_compatible_htile);
+ rtex->tc_compatible_htile = rtex->surface.htile_size != 0 &&
+ (rtex->surface.flags &
+ RADEON_SURF_TC_COMPATIBLE_HTILE);
/* TC-compatible HTILE only supports Z32_FLOAT. */
if (rtex->tc_compatible_htile)
/* Now create the backing buffer. */
if (!buf) {
r600_init_resource_fields(rscreen, resource, rtex->size,
- rtex->surface.bo_alignment);
+ rtex->surface.surf_alignment);
resource->flags |= RADEON_FLAG_HANDLE;
/* Initialize the cmask to 0xCC (= compressed state). */
r600_screen_clear_buffer(rscreen, &rtex->cmask_buffer->b.b,
rtex->cmask.offset, rtex->cmask.size,
- 0xCCCCCCCC, R600_COHERENCY_NONE);
+ 0xCCCCCCCC);
}
/* Initialize DCC only if the texture is not being imported. */
r600_screen_clear_buffer(rscreen, &rtex->resource.b.b,
rtex->dcc_offset,
rtex->surface.dcc_size,
- 0xFFFFFFFF, R600_COHERENCY_NONE);
+ 0xFFFFFFFF);
}
/* Initialize the CMASK base register value. */
/* Textures with a very small height are recommended to be linear. */
if (templ->target == PIPE_TEXTURE_1D ||
templ->target == PIPE_TEXTURE_1D_ARRAY ||
- templ->height0 <= 4)
+ /* Only very thin and long 2D textures should benefit from
+ * linear_aligned. */
+ (templ->width0 > 8 && templ->height0 <= 2))
return RADEON_SURF_MODE_LINEAR_ALIGNED;
/* Textures likely to be mapped often. */
/* There is no point in discarding depth and tiled buffers. */
assert(!rtex->is_depth);
- assert(rtex->surface.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED);
+ assert(rtex->surface.is_linear);
/* Reallocate the buffer in the same pipe_resource. */
r600_alloc_resource(rscreen, &rtex->resource);
rtex->cmask.base_address_reg =
(rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
- r600_dirty_all_framebuffer_states(rscreen);
- p_atomic_inc(&rscreen->dirty_tex_descriptor_counter);
+ p_atomic_inc(&rscreen->dirty_tex_counter);
rctx->num_alloc_tex_transfer_bytes += rtex->size;
}
bool use_staging_texture = false;
assert(!(texture->flags & R600_RESOURCE_FLAG_TRANSFER));
+ assert(box->width && box->height && box->depth);
/* Depth textures use staging unconditionally. */
if (!rtex->is_depth) {
/* Tiled textures need to be converted into a linear texture for CPU
* access. The staging texture is always linear and is placed in GART.
*
- * Reading from VRAM is slow, always use the staging texture in
- * this case.
+ * Reading from VRAM or GTT WC is slow, always use the staging
+ * texture in this case.
*
* Use the staging texture for uploads if the underlying BO
* is busy.
*/
- if (rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D)
+ if (!rtex->surface.is_linear)
use_staging_texture = true;
else if (usage & PIPE_TRANSFER_READ)
- use_staging_texture = (rtex->resource.domains &
- RADEON_DOMAIN_VRAM) != 0;
+ use_staging_texture =
+ rtex->resource.domains & RADEON_DOMAIN_VRAM ||
+ rtex->resource.flags & RADEON_FLAG_GTT_WC;
/* Write & linear only: */
else if (r600_rings_is_buffer_referenced(rctx, rtex->resource.buf,
RADEON_USAGE_READWRITE) ||
trans = CALLOC_STRUCT(r600_transfer);
if (!trans)
return NULL;
- trans->transfer.resource = texture;
+ pipe_resource_reference(&trans->transfer.resource, texture);
trans->transfer.level = level;
trans->transfer.usage = usage;
trans->transfer.box = *box;
offset = r600_texture_get_offset(staging_depth, level, box);
}
- trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes;
+ trans->transfer.stride = staging_depth->surface.level[level].nblk_x *
+ staging_depth->surface.bpe;
trans->transfer.layer_stride = staging_depth->surface.level[level].slice_size;
trans->staging = (struct r600_resource*)staging_depth;
buf = trans->staging;
return NULL;
}
trans->staging = &staging->resource;
- trans->transfer.stride = staging->surface.level[0].pitch_bytes;
+ trans->transfer.stride = staging->surface.level[0].nblk_x *
+ staging->surface.bpe;
trans->transfer.layer_stride = staging->surface.level[0].slice_size;
if (usage & PIPE_TRANSFER_READ)
buf = trans->staging;
} else {
/* the resource is mapped directly */
- trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
+ trans->transfer.stride = rtex->surface.level[level].nblk_x *
+ rtex->surface.bpe;
trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
offset = r600_texture_get_offset(rtex, level, box);
buf = &rtex->resource;
rctx->num_alloc_tex_transfer_bytes = 0;
}
+ pipe_resource_reference(&transfer->resource, NULL);
FREE(transfer);
}
struct r600_texture *rtex = (struct r600_texture *)tex;
if (rtex->dcc_offset &&
- rtex->surface.level[level].dcc_enabled &&
+ level < rtex->surface.num_dcc_levels &&
!vi_dcc_formats_compatible(tex->format, view_format))
if (!r600_texture_disable_dcc(rctx, (struct r600_texture*)tex))
rctx->decompress_dcc(&rctx->b, rtex);
unsigned width, unsigned height)
{
struct r600_common_context *rctx = (struct r600_common_context*)pipe;
- struct r600_texture *rtex = (struct r600_texture*)texture;
struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
if (!surface)
surface->base.width = width;
surface->base.height = height;
surface->base.u = templ->u;
- surface->level_info = &rtex->surface.level[templ->u.tex.level];
if (texture->target != PIPE_BUFFER)
vi_dcc_disable_if_incompatible_format(rctx, texture,
if (!vi_should_enable_separate_dcc(tex))
return; /* stats show that DCC decompression is too expensive */
- assert(tex->surface.level[0].dcc_enabled);
+ assert(tex->surface.num_dcc_levels);
assert(!tex->dcc_separate_buffer);
r600_texture_discard_cmask(rctx->screen, tex);
tex->last_dcc_separate_buffer = NULL;
} else {
tex->dcc_separate_buffer = (struct r600_resource*)
- r600_aligned_buffer_create(rctx->b.screen, 0,
+ r600_aligned_buffer_create(rctx->b.screen,
+ R600_RESOURCE_FLAG_UNMAPPABLE,
PIPE_USAGE_DEFAULT,
tex->surface.dcc_size,
tex->surface.dcc_alignment);
memset(&uc, 0, sizeof(uc));
- if (util_format_get_blocksizebits(surface_format) == 128) {
+ if (rtex->surface.bpe == 16) {
/* DCC fast clear only:
* CLEAR_WORD0 = R = G = B
* CLEAR_WORD1 = A
struct pipe_resource *dcc_buffer;
uint64_t dcc_offset;
- assert(rtex->dcc_offset && rtex->surface.level[level].dcc_enabled);
+ assert(rtex->dcc_offset && level < rtex->surface.num_dcc_levels);
if (rtex->dcc_separate_buffer) {
dcc_buffer = &rtex->dcc_separate_buffer->b.b;
*/
if (rscreen->chip_class >= CIK) {
switch (rtex->last_msaa_resolve_target_micro_mode) {
- case 0: /* displayable */
+ case RADEON_MICRO_MODE_DISPLAY:
rtex->surface.tiling_index[0] = 10;
break;
- case 1: /* thin */
+ case RADEON_MICRO_MODE_THIN:
rtex->surface.tiling_index[0] = 14;
break;
- case 3: /* rotated */
+ case RADEON_MICRO_MODE_ROTATED:
rtex->surface.tiling_index[0] = 28;
break;
default: /* depth, thick */
}
} else { /* SI */
switch (rtex->last_msaa_resolve_target_micro_mode) {
- case 0: /* displayable */
+ case RADEON_MICRO_MODE_DISPLAY:
switch (rtex->surface.bpe) {
case 1:
rtex->surface.tiling_index[0] = 10;
break;
}
break;
- case 1: /* thin */
+ case RADEON_MICRO_MODE_THIN:
switch (rtex->surface.bpe) {
case 1:
rtex->surface.tiling_index[0] = 14;
rtex->surface.micro_tile_mode = rtex->last_msaa_resolve_target_micro_mode;
- p_atomic_inc(&rscreen->dirty_fb_counter);
- p_atomic_inc(&rscreen->dirty_tex_descriptor_counter);
+ p_atomic_inc(&rscreen->dirty_tex_counter);
}
void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
}
/* only supported on tiled surfaces */
- if (tex->surface.level[0].mode < RADEON_SURF_MODE_1D) {
+ if (tex->surface.is_linear) {
continue;
}
continue;
/* fast color clear with 1D tiling doesn't work on old kernels and CIK */
- if (tex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
- rctx->chip_class >= CIK &&
+ if (rctx->chip_class == CIK &&
+ tex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
rctx->screen->info.drm_major == 2 &&
rctx->screen->info.drm_minor < 38) {
continue;
}
/* Try to clear DCC first, otherwise try CMASK. */
- if (tex->dcc_offset && tex->surface.level[0].dcc_enabled) {
+ if (tex->dcc_offset && tex->surface.num_dcc_levels) {
uint32_t reset_value;
bool clear_words_needed;
tex->separate_dcc_dirty = true;
} else {
/* 128-bit formats are unusupported */
- if (util_format_get_blocksizebits(fb->cbufs[i]->format) > 64) {
+ if (tex->surface.bpe > 8) {
continue;
}
projects / mesa.git / blobdiff