}
static int r600_init_surface(struct r600_common_screen *rscreen,
- struct radeon_surface *surface,
+ struct radeon_surf *surface,
const struct pipe_resource *ptex,
unsigned array_mode,
bool is_flushed_depth)
{
struct r600_texture *rtex = (struct r600_texture*)ptex;
struct r600_resource *resource = &rtex->resource;
- struct radeon_surface *surface = &rtex->surface;
+ struct radeon_surf *surface = &rtex->surface;
struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
rscreen->ws->buffer_set_tiling(resource->buf,
RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
surface->level[0].mode >= RADEON_SURF_MODE_2D ?
RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
+ surface->pipe_config,
surface->bankw, surface->bankh,
surface->tile_split,
surface->stencil_tile_split,
- surface->mtilea,
+ surface->mtilea, surface->num_banks,
surface->level[0].pitch_bytes,
(surface->flags & RADEON_SURF_SCANOUT) != 0);
if (rtex->cmask_buffer != &rtex->resource) {
pipe_resource_reference((struct pipe_resource**)&rtex->cmask_buffer, NULL);
}
+ pipe_resource_reference((struct pipe_resource**)&rtex->dcc_buffer, NULL);
pb_reference(&resource->buf, NULL);
FREE(rtex);
}
struct r600_fmask_info *out)
{
/* FMASK is allocated like an ordinary texture. */
- struct radeon_surface fmask = rtex->surface;
+ struct radeon_surf fmask = rtex->surface;
memset(out, 0, sizeof(*out));
rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
}
+static void vi_texture_alloc_dcc_separate(struct r600_common_screen *rscreen,
+ struct r600_texture *rtex)
+{
+ if (rscreen->debug_flags & DBG_NO_DCC)
+ return;
+
+ rtex->dcc_buffer = (struct r600_resource *)
+ r600_aligned_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
+ PIPE_USAGE_DEFAULT, rtex->surface.dcc_size, rtex->surface.dcc_alignment);
+ if (rtex->dcc_buffer == NULL) {
+ return;
+ }
+
+ r600_screen_clear_buffer(rscreen, &rtex->dcc_buffer->b.b, 0, rtex->surface.dcc_size,
+ 0xFFFFFFFF, true);
+
+ rtex->cb_color_info |= VI_S_028C70_DCC_ENABLE(1);
+}
+
static unsigned r600_texture_get_htile_size(struct r600_common_screen *rscreen,
struct r600_texture *rtex)
{
unsigned num_pipes = rscreen->tiling_info.num_channels;
if (rscreen->chip_class <= EVERGREEN &&
- rscreen->info.drm_minor < 26)
+ rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 26)
return 0;
/* HW bug on R6xx. */
/* HTILE is broken with 1D tiling on old kernels and CIK. */
if (rscreen->chip_class >= CIK &&
rtex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
- rscreen->info.drm_minor < 38)
+ rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 38)
return 0;
switch (num_pipes) {
* without htile buffer */
R600_ERR("Failed to create buffer object for htile buffer.\n");
} else {
- /* Clear to fully-expanded state. */
r600_screen_clear_buffer(rscreen, &rtex->htile_buffer->b.b, 0,
- htile_size, 0xffffffff);
+ htile_size, 0, true);
}
}
const struct pipe_resource *base,
unsigned pitch_in_bytes_override,
struct pb_buffer *buf,
- struct radeon_surface *surface)
+ struct radeon_surf *surface)
{
struct r600_texture *rtex;
struct r600_resource *resource;
if (rtex->is_depth) {
if (!(base->flags & (R600_RESOURCE_FLAG_TRANSFER |
R600_RESOURCE_FLAG_FLUSHED_DEPTH)) &&
- (rscreen->debug_flags & DBG_HYPERZ)) {
+ !(rscreen->debug_flags & DBG_NO_HYPERZ)) {
r600_texture_allocate_htile(rscreen, rtex);
}
return NULL;
}
}
+ if (rtex->surface.dcc_size)
+ vi_texture_alloc_dcc_separate(rscreen, rtex);
}
/* Now create the backing buffer. */
if (rtex->cmask.size) {
/* Initialize the cmask to 0xCC (= compressed state). */
r600_screen_clear_buffer(rscreen, &rtex->cmask_buffer->b.b,
- rtex->cmask.offset, rtex->cmask.size, 0xCCCCCCCC);
+ rtex->cmask.offset, rtex->cmask.size,
+ 0xCCCCCCCC, true);
}
/* Initialize the CMASK base register value. */
const struct pipe_resource *templ)
{
const struct util_format_description *desc = util_format_description(templ->format);
+ bool force_tiling = templ->flags & R600_RESOURCE_FLAG_FORCE_TILING;
/* MSAA resources must be 2D tiled. */
if (templ->nr_samples > 1)
if (templ->flags & R600_RESOURCE_FLAG_TRANSFER)
return RADEON_SURF_MODE_LINEAR_ALIGNED;
+ /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
+ if (rscreen->chip_class >= R600 && rscreen->chip_class <= CAYMAN &&
+ (templ->bind & PIPE_BIND_COMPUTE_RESOURCE) &&
+ (templ->target == PIPE_TEXTURE_2D ||
+ templ->target == PIPE_TEXTURE_3D))
+ force_tiling = true;
+
/* Handle common candidates for the linear mode.
* Compressed textures must always be tiled. */
- if (!(templ->flags & R600_RESOURCE_FLAG_FORCE_TILING) &&
- !util_format_is_compressed(templ->format)) {
+ if (!force_tiling && !util_format_is_compressed(templ->format)) {
/* Not everything can be linear, so we cannot enforce it
* for all textures. */
if ((rscreen->debug_flags & DBG_NO_TILING) &&
const struct pipe_resource *templ)
{
struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
- struct radeon_surface surface = {0};
+ struct radeon_surf surface = {0};
int r;
r = r600_init_surface(rscreen, &surface, templ,
unsigned stride = 0;
unsigned array_mode;
enum radeon_bo_layout micro, macro;
- struct radeon_surface surface;
+ struct radeon_surf surface;
bool scanout;
int r;
* the CPU is much happier reading out of cached system memory
* than uncached VRAM.
*/
- if (rtex->surface.level[level].mode >= RADEON_SURF_MODE_1D)
+ if (rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D) {
use_staging_texture = TRUE;
-
- /* Untiled buffers in VRAM, which is slow for CPU reads */
- if ((usage & PIPE_TRANSFER_READ) && !(usage & PIPE_TRANSFER_MAP_DIRECTLY) &&
+ } else if ((usage & PIPE_TRANSFER_READ) && !(usage & PIPE_TRANSFER_MAP_DIRECTLY) &&
(rtex->resource.domains == RADEON_DOMAIN_VRAM)) {
+ /* Untiled buffers in VRAM, which is slow for CPU reads */
use_staging_texture = TRUE;
- }
-
- /* Use a staging texture for uploads if the underlying BO is busy. */
- if (!(usage & PIPE_TRANSFER_READ) &&
+ } else if (!(usage & PIPE_TRANSFER_READ) &&
(r600_rings_is_buffer_referenced(rctx, rtex->resource.cs_buf, RADEON_USAGE_READWRITE) ||
- rctx->ws->buffer_is_busy(rtex->resource.buf, RADEON_USAGE_READWRITE))) {
+ !rctx->ws->buffer_wait(rtex->resource.buf, 0, RADEON_USAGE_READWRITE))) {
+ /* Use a staging texture for uploads if the underlying BO is busy. */
use_staging_texture = TRUE;
}
if (usage & PIPE_TRANSFER_READ) {
struct pipe_resource *temp = ctx->screen->resource_create(ctx->screen, &resource);
+ if (!temp) {
+ R600_ERR("failed to create a temporary depth texture\n");
+ FREE(trans);
+ return NULL;
+ }
r600_copy_region_with_blit(ctx, temp, 0, 0, 0, 0, texture, level, box);
rctx->blit_decompress_depth(ctx, (struct r600_texture*)temp, staging_depth,
struct pipe_transfer* transfer)
{
struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
- struct r600_common_context *rctx = (struct r600_common_context*)ctx;
- struct radeon_winsys_cs_handle *buf;
struct pipe_resource *texture = transfer->resource;
struct r600_texture *rtex = (struct r600_texture*)texture;
- if (rtransfer->staging) {
- buf = rtransfer->staging->cs_buf;
- } else {
- buf = r600_resource(transfer->resource)->cs_buf;
- }
- rctx->ws->buffer_unmap(buf);
-
if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
if (rtex->is_depth && rtex->resource.b.b.nr_samples <= 1) {
ctx->resource_copy_region(ctx, texture, transfer->level,
NULL, /* get_handle */
r600_texture_destroy, /* resource_destroy */
r600_texture_transfer_map, /* transfer_map */
- NULL, /* transfer_flush_region */
+ u_default_transfer_flush_region, /* transfer_flush_region */
r600_texture_transfer_unmap, /* transfer_unmap */
NULL /* transfer_inline_write */
};
memcpy(rtex->color_clear_value, &uc, 2 * sizeof(uint32_t));
}
+static void vi_get_fast_clear_parameters(enum pipe_format surface_format,
+ const union pipe_color_union *color,
+ uint32_t* reset_value,
+ bool* clear_words_needed)
+{
+ bool values[4] = {};
+ int i;
+ bool main_value = false;
+ bool extra_value = false;
+ int extra_channel;
+ const struct util_format_description *desc = util_format_description(surface_format);
+
+ *clear_words_needed = true;
+ *reset_value = 0x20202020U;
+
+ /* If we want to clear without needing a fast clear eliminate step, we
+ * can set each channel to 0 or 1 (or 0/max for integer formats). We
+ * have two sets of flags, one for the last or first channel(extra) and
+ * one for the other channels(main).
+ */
+
+ if (surface_format == PIPE_FORMAT_R11G11B10_FLOAT ||
+ surface_format == PIPE_FORMAT_B5G6R5_UNORM ||
+ surface_format == PIPE_FORMAT_B5G6R5_SRGB) {
+ extra_channel = -1;
+ } else if (desc->layout == UTIL_FORMAT_LAYOUT_PLAIN) {
+ if(r600_translate_colorswap(surface_format) <= 1)
+ extra_channel = desc->nr_channels - 1;
+ else
+ extra_channel = 0;
+ } else
+ return;
+
+ for (i = 0; i < 4; ++i) {
+ int index = desc->swizzle[i] - UTIL_FORMAT_SWIZZLE_X;
+
+ if (desc->swizzle[i] < UTIL_FORMAT_SWIZZLE_X ||
+ desc->swizzle[i] > UTIL_FORMAT_SWIZZLE_W)
+ continue;
+
+ if (util_format_is_pure_sint(surface_format)) {
+ values[i] = color->i[i] != 0;
+ if (color->i[i] != 0 && color->i[i] != INT32_MAX)
+ return;
+ } else if (util_format_is_pure_uint(surface_format)) {
+ values[i] = color->ui[i] != 0U;
+ if (color->ui[i] != 0U && color->ui[i] != UINT32_MAX)
+ return;
+ } else {
+ values[i] = color->f[i] != 0.0F;
+ if (color->f[i] != 0.0F && color->f[i] != 1.0F)
+ return;
+ }
+
+ if (index == extra_channel)
+ extra_value = values[i];
+ else
+ main_value = values[i];
+ }
+
+ for (int i = 0; i < 4; ++i)
+ if (values[i] != main_value &&
+ desc->swizzle[i] - UTIL_FORMAT_SWIZZLE_X != extra_channel &&
+ desc->swizzle[i] >= UTIL_FORMAT_SWIZZLE_X &&
+ desc->swizzle[i] <= UTIL_FORMAT_SWIZZLE_W)
+ return;
+
+ *clear_words_needed = false;
+ if (main_value)
+ *reset_value |= 0x80808080U;
+
+ if (extra_value)
+ *reset_value |= 0x40404040U;
+}
+
void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
struct pipe_framebuffer_state *fb,
struct r600_atom *fb_state,
- unsigned *buffers,
+ unsigned *buffers, unsigned *dirty_cbufs,
const union pipe_color_union *color)
{
int i;
/* fast color clear with 1D tiling doesn't work on old kernels and CIK */
if (tex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
- rctx->chip_class >= CIK && rctx->screen->info.drm_minor < 38) {
+ rctx->chip_class >= CIK &&
+ rctx->screen->info.drm_major == 2 &&
+ rctx->screen->info.drm_minor < 38) {
continue;
}
- /* ensure CMASK is enabled */
- r600_texture_alloc_cmask_separate(rctx->screen, tex);
- if (tex->cmask.size == 0) {
- continue;
+ if (tex->dcc_buffer) {
+ uint32_t reset_value;
+ bool clear_words_needed;
+
+ if (rctx->screen->debug_flags & DBG_NO_DCC_CLEAR)
+ continue;
+
+ vi_get_fast_clear_parameters(fb->cbufs[i]->format, color, &reset_value, &clear_words_needed);
+
+ rctx->clear_buffer(&rctx->b, &tex->dcc_buffer->b.b,
+ 0, tex->surface.dcc_size, reset_value, true);
+
+ if (clear_words_needed)
+ tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
+ } else {
+ /* ensure CMASK is enabled */
+ r600_texture_alloc_cmask_separate(rctx->screen, tex);
+ if (tex->cmask.size == 0) {
+ continue;
+ }
+
+ /* Do the fast clear. */
+ rctx->clear_buffer(&rctx->b, &tex->cmask_buffer->b.b,
+ tex->cmask.offset, tex->cmask.size, 0, true);
+
+ tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
}
- /* Do the fast clear. */
evergreen_set_clear_color(tex, fb->cbufs[i]->format, color);
- rctx->clear_buffer(&rctx->b, &tex->cmask_buffer->b.b,
- tex->cmask.offset, tex->cmask.size, 0);
- tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
- fb_state->dirty = true;
+ if (dirty_cbufs)
+ *dirty_cbufs |= 1 << i;
+ rctx->set_atom_dirty(rctx, fb_state, true);
*buffers &= ~clear_bit;
}
}
projects / mesa.git / blobdiff