#define R600_CONFIG_REG_OFFSET 0x08000
#define R600_CONTEXT_REG_OFFSET 0x28000
+#define SI_SH_REG_OFFSET 0x0000B000
+#define SI_SH_REG_END 0x0000C000
#define CIK_UCONFIG_REG_OFFSET 0x00030000
-#define CIK_UCONFIG_REG_END 0x00031000
+#define CIK_UCONFIG_REG_END 0x00038000
#define PKT_TYPE_S(x) (((x) & 0x3) << 30)
#define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
#define STRMOUT_SELECT_BUFFER(x) (((x) & 0x3) << 8)
#define PKT3_WAIT_REG_MEM 0x3C
#define WAIT_REG_MEM_EQUAL 3
+#define WAIT_REG_MEM_MEM_SPACE(x) (((x) & 0x3) << 4)
#define PKT3_EVENT_WRITE 0x46
#define PKT3_EVENT_WRITE_EOP 0x47
+#define EOP_DATA_SEL(x) ((x) << 29)
+ /* 0 - discard
+ * 1 - send low 32bit data
+ * 2 - send 64bit data
+ * 3 - send 64bit GPU counter value
+ * 4 - send 64bit sys counter value
+ */
#define PKT3_SET_CONFIG_REG 0x68
#define PKT3_SET_CONTEXT_REG 0x69
#define PKT3_STRMOUT_BASE_UPDATE 0x72 /* r700 only */
#define SURFACE_BASE_UPDATE_COLOR(x) (2 << (x))
#define SURFACE_BASE_UPDATE_COLOR_NUM(x) (((1 << x) - 1) << 1)
#define SURFACE_BASE_UPDATE_STRMOUT(x) (0x200 << (x))
-#define PKT3_SET_UCONFIG_REG 0x79 /* new for CIK */
+#define PKT3_SET_SH_REG 0x76 /* SI and later */
+#define PKT3_SET_UCONFIG_REG 0x79 /* CIK and later */
+#define EVENT_TYPE_SAMPLE_STREAMOUTSTATS1 0x1 /* EG and later */
+#define EVENT_TYPE_SAMPLE_STREAMOUTSTATS2 0x2 /* EG and later */
+#define EVENT_TYPE_SAMPLE_STREAMOUTSTATS3 0x3 /* EG and later */
#define EVENT_TYPE_PS_PARTIAL_FLUSH 0x10
#define EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT 0x14
#define EVENT_TYPE_ZPASS_DONE 0x15
#define EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT 0x16
+#define EVENT_TYPE_PERFCOUNTER_START 0x17
+#define EVENT_TYPE_PERFCOUNTER_STOP 0x18
#define EVENT_TYPE_PIPELINESTAT_START 25
#define EVENT_TYPE_PIPELINESTAT_STOP 26
+#define EVENT_TYPE_PERFCOUNTER_SAMPLE 0x1B
#define EVENT_TYPE_SAMPLE_PIPELINESTAT 30
#define EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH 0x1f
#define EVENT_TYPE_SAMPLE_STREAMOUTSTATS 0x20
#define C_028B20_BUFFER_3_EN 0xFFFFFFF7
#define R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 0x028AD0
+#define V_0280A0_SWAP_STD 0x00000000
+#define V_0280A0_SWAP_ALT 0x00000001
+#define V_0280A0_SWAP_STD_REV 0x00000002
+#define V_0280A0_SWAP_ALT_REV 0x00000003
+
/* EG+ */
#define R_0084FC_CP_STRMOUT_CNTL 0x0084FC
#define S_0084FC_OFFSET_UPDATE_DONE(x) (((x) & 0x1) << 0)
#define G_028B98_STREAM_3_BUFFER_EN(x) (((x) >> 12) & 0x0F)
#define C_028B98_STREAM_3_BUFFER_EN 0xFFFF0FFF
+#define EG_R_028A4C_PA_SC_MODE_CNTL_1 0x028A4C
+#define EG_S_028A4C_PS_ITER_SAMPLE(x) (((x) & 0x1) << 16)
+#define EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(x) (((x) & 0x1) << 25)
+#define EG_S_028A4C_FORCE_EOV_REZ_ENABLE(x) (((x) & 0x1) << 26)
+
+#define CM_R_028804_DB_EQAA 0x00028804
+#define S_028804_MAX_ANCHOR_SAMPLES(x) (((x) & 0x7) << 0)
+#define S_028804_PS_ITER_SAMPLES(x) (((x) & 0x7) << 4)
+#define S_028804_MASK_EXPORT_NUM_SAMPLES(x) (((x) & 0x7) << 8)
+#define S_028804_ALPHA_TO_MASK_NUM_SAMPLES(x) (((x) & 0x7) << 12)
+#define S_028804_HIGH_QUALITY_INTERSECTIONS(x) (((x) & 0x1) << 16)
+#define S_028804_INCOHERENT_EQAA_READS(x) (((x) & 0x1) << 17)
+#define S_028804_INTERPOLATE_COMP_Z(x) (((x) & 0x1) << 18)
+#define S_028804_INTERPOLATE_SRC_Z(x) (((x) & 0x1) << 19)
+#define S_028804_STATIC_ANCHOR_ASSOCIATIONS(x) (((x) & 0x1) << 20)
+#define S_028804_ALPHA_TO_MASK_EQAA_DISABLE(x) (((x) & 0x1) << 21)
+#define S_028804_OVERRASTERIZATION_AMOUNT(x) (((x) & 0x07) << 24)
+#define S_028804_ENABLE_POSTZ_OVERRASTERIZATION(x) (((x) & 0x1) << 27)
+#define CM_R_028BDC_PA_SC_LINE_CNTL 0x28bdc
+#define S_028BDC_EXPAND_LINE_WIDTH(x) (((x) & 0x1) << 9)
+#define G_028BDC_EXPAND_LINE_WIDTH(x) (((x) >> 9) & 0x1)
+#define C_028BDC_EXPAND_LINE_WIDTH 0xFFFFFDFF
+#define S_028BDC_LAST_PIXEL(x) (((x) & 0x1) << 10)
+#define G_028BDC_LAST_PIXEL(x) (((x) >> 10) & 0x1)
+#define C_028BDC_LAST_PIXEL 0xFFFFFBFF
+#define CM_R_028BE0_PA_SC_AA_CONFIG 0x28be0
+#define S_028BE0_MSAA_NUM_SAMPLES(x) (((x) & 0x7) << 0)
+#define S_028BE0_AA_MASK_CENTROID_DTMN(x) (((x) & 0x1) << 4)
+#define S_028BE0_MAX_SAMPLE_DIST(x) (((x) & 0xf) << 13)
+#define S_028BE0_MSAA_EXPOSED_SAMPLES(x) (((x) & 0x7) << 20)
+#define S_028BE0_DETAIL_TO_EXPOSED_MODE(x) (((x) & 0x3) << 24)
+#define CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0x28bf8
+#define CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0x28c08
+#define CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0x28c18
+#define CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0x28c28
+
+#define EG_S_028C70_FAST_CLEAR(x) (((x) & 0x1) << 17)
+#define SI_S_028C70_FAST_CLEAR(x) (((x) & 0x1) << 13)
+#define VI_S_028C70_DCC_ENABLE(x) (((x) & 0x1) << 28)
+
/*CIK+*/
#define R_0300FC_CP_STRMOUT_CNTL 0x0300FC
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