#include "gallivm/lp_bld_init.h"
#include "gallivm/lp_bld_tgsi.h"
-#define RADEON_LLVM_MAX_INPUTS 16 * 4
-#define RADEON_LLVM_MAX_OUTPUTS 16 * 4
-#define RADEON_LLVM_MAX_BRANCH_DEPTH 16
-#define RADEON_LLVM_MAX_LOOP_DEPTH 16
+#define RADEON_LLVM_MAX_INPUTS 32 * 4
+#define RADEON_LLVM_MAX_OUTPUTS 32 * 4
+
+#define RADEON_LLVM_INITIAL_CF_DEPTH 4
#define RADEON_LLVM_MAX_SYSTEM_VALUES 4
unsigned chip_class;
unsigned type;
- unsigned face_input;
+ unsigned face_gpr;
unsigned two_side;
+ unsigned inputs_count;
struct r600_shader_io * r600_inputs;
struct r600_shader_io * r600_outputs;
+ struct pipe_stream_output_info *stream_outputs;
unsigned color_buffer_count;
unsigned fs_color_all;
+ unsigned alpha_to_one;
+ unsigned has_txq_cube_array_z_comp;
+ unsigned uses_tex_buffers;
+ unsigned has_compressed_msaa_texturing;
/*=== Front end configuration ===*/
- /* Special Intrinsics */
-
- /** Write to an output register: float store_output(float, i32) */
- const char * store_output_intr;
-
- /** Swizzle a vector value: <4 x float> swizzle(<4 x float>, i32)
- * The swizzle is an unsigned integer that encodes a TGSI_SWIZZLE_* value
- * in 2-bits.
- * Swizzle{0-1} = X Channel
- * Swizzle{2-3} = Y Channel
- * Swizzle{4-5} = Z Channel
- * Swizzle{6-7} = W Channel
- */
- const char * swizzle_intr;
-
/* Instructions that are not described by any of the TGSI opcodes. */
/** This function is responsible for initilizing the inputs array and will be
unsigned index,
const struct tgsi_full_declaration *decl);
- /** User data to use with the callbacks */
- void * userdata;
-
/** This array contains the input values for the shader. Typically these
* values will be in the form of a target intrinsic that will inform the
* backend how to load the actual inputs to the shader.
LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS][TGSI_NUM_CHANNELS];
unsigned output_reg_count;
+ /** This pointer is used to contain the temporary values.
+ * The amount of temporary used in tgsi can't be bound to a max value and
+ * thus we must allocate this array at runtime.
+ */
+ LLVMValueRef *temps;
+ unsigned temps_count;
LLVMValueRef system_values[RADEON_LLVM_MAX_SYSTEM_VALUES];
- unsigned reserved_reg_count;
/*=== Private Members ===*/
- struct radeon_llvm_branch branch[RADEON_LLVM_MAX_BRANCH_DEPTH];
- struct radeon_llvm_loop loop[RADEON_LLVM_MAX_LOOP_DEPTH];
+ struct radeon_llvm_branch *branch;
+ struct radeon_llvm_loop *loop;
unsigned branch_depth;
+ unsigned branch_depth_max;
unsigned loop_depth;
+ unsigned loop_depth_max;
+ struct tgsi_declaration_range *arrays;
LLVMValueRef main_fn;
struct gallivm_state gallivm;
};
-static inline LLVMValueRef bitcast(
+static inline LLVMTypeRef tgsi2llvmtype(
struct lp_build_tgsi_context * bld_base,
- enum tgsi_opcode_type type,
- LLVMValueRef value
-)
+ enum tgsi_opcode_type type)
{
- LLVMBuilderRef builder = bld_base->base.gallivm->builder;
LLVMContextRef ctx = bld_base->base.gallivm->context;
- LLVMTypeRef dst_type;
switch (type) {
case TGSI_TYPE_UNSIGNED:
case TGSI_TYPE_SIGNED:
- dst_type = LLVMInt32TypeInContext(ctx);
- break;
+ return LLVMInt32TypeInContext(ctx);
+ case TGSI_TYPE_DOUBLE:
+ return LLVMDoubleTypeInContext(ctx);
case TGSI_TYPE_UNTYPED:
case TGSI_TYPE_FLOAT:
- dst_type = LLVMFloatTypeInContext(ctx);
- break;
- default:
- dst_type = 0;
- break;
+ return LLVMFloatTypeInContext(ctx);
+ default: break;
}
+ return 0;
+}
+
+static inline LLVMValueRef bitcast(
+ struct lp_build_tgsi_context * bld_base,
+ enum tgsi_opcode_type type,
+ LLVMValueRef value
+)
+{
+ LLVMBuilderRef builder = bld_base->base.gallivm->builder;
+ LLVMTypeRef dst_type = tgsi2llvmtype(bld_base, type);
if (dst_type)
return LLVMBuildBitCast(builder, value, dst_type, "");
void radeon_llvm_emit_prepare_cube_coords(struct lp_build_tgsi_context * bld_base,
- LLVMValueRef *arg, unsigned target);
+ struct lp_build_emit_data * emit_data,
+ LLVMValueRef *coords_arg,
+ LLVMValueRef *derivs_arg);
void radeon_llvm_context_init(struct radeon_llvm_context * ctx);
+void radeon_llvm_create_func(struct radeon_llvm_context * ctx,
+ LLVMTypeRef *ParamTypes, unsigned ParamCount);
+
void radeon_llvm_dispose(struct radeon_llvm_context * ctx);
inline static struct radeon_llvm_context * radeon_llvm_context(
void radeon_llvm_finalize_module(struct radeon_llvm_context * ctx);
-LLVMValueRef
-build_intrinsic(LLVMBuilderRef builder,
- const char *name,
- LLVMTypeRef ret_type,
- LLVMValueRef *args,
- unsigned num_args,
- LLVMAttribute attr);
-
void
build_tgsi_intrinsic_nomem(
const struct lp_build_tgsi_action * action,
struct lp_build_tgsi_context * bld_base,
struct lp_build_emit_data * emit_data);
-
+LLVMValueRef
+radeon_llvm_emit_fetch_double(struct lp_build_tgsi_context *bld_base,
+ LLVMValueRef ptr,
+ LLVMValueRef ptr2);
+
+LLVMValueRef radeon_llvm_saturate(struct lp_build_tgsi_context *bld_base,
+ LLVMValueRef value);
+
+LLVMValueRef radeon_llvm_emit_fetch(struct lp_build_tgsi_context *bld_base,
+ const struct tgsi_full_src_register *reg,
+ enum tgsi_opcode_type type,
+ unsigned swizzle);
+
+void radeon_llvm_emit_store(
+ struct lp_build_tgsi_context * bld_base,
+ const struct tgsi_full_instruction * inst,
+ const struct tgsi_opcode_info * info,
+ LLVMValueRef dst[4]);
#endif /* RADEON_LLVM_H */
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