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gallium/drivers: Sanitize NULL checks into canonical form
[mesa.git] / src / gallium / drivers / radeon / radeon_setup_tgsi_llvm.c
diff --git a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
index 91cf6587181022605ee9054f0d5330cf9f6b0d8a..c94f1093ab7d4cc3c5a9dfe51b84adc943610d9f 100644 (file)
--- a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
+++ b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
@@ -919,7 +919,21 @@ static void emit_ucmp(
                LLVMBuildSelect(builder, v, emit_data->args[1], emit_data->args[2], "");
 }
 
-static void emit_cmp(
+static void emit_cmp(const struct lp_build_tgsi_action *action,
+                    struct lp_build_tgsi_context *bld_base,
+                    struct lp_build_emit_data *emit_data)
+{
+       LLVMBuilderRef builder = bld_base->base.gallivm->builder;
+       LLVMValueRef cond, *args = emit_data->args;
+
+       cond = LLVMBuildFCmp(builder, LLVMRealOLT, args[0],
+                            bld_base->base.zero, "");
+
+       emit_data->output[emit_data->chan] =
+               LLVMBuildSelect(builder, cond, args[1], args[2], "");
+}
+
+static void emit_set_cond(
                const struct lp_build_tgsi_action *action,
                struct lp_build_tgsi_context * bld_base,
                struct lp_build_emit_data * emit_data)
@@ -1393,6 +1407,51 @@ static void emit_imsb(const struct lp_build_tgsi_action * action,
                LLVMBuildSelect(builder, cond, all_ones, msb, "");
 }
 
+static void emit_iabs(const struct lp_build_tgsi_action *action,
+                     struct lp_build_tgsi_context *bld_base,
+                     struct lp_build_emit_data *emit_data)
+{
+       LLVMBuilderRef builder = bld_base->base.gallivm->builder;
+
+       emit_data->output[emit_data->chan] =
+               lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_IMAX,
+                                         emit_data->args[0],
+                                         LLVMBuildNeg(builder,
+                                                      emit_data->args[0], ""));
+}
+
+static void emit_minmax_int(const struct lp_build_tgsi_action *action,
+                           struct lp_build_tgsi_context *bld_base,
+                           struct lp_build_emit_data *emit_data)
+{
+       LLVMBuilderRef builder = bld_base->base.gallivm->builder;
+       LLVMIntPredicate op;
+
+       switch (emit_data->info->opcode) {
+       default:
+               assert(0);
+       case TGSI_OPCODE_IMAX:
+               op = LLVMIntSGT;
+               break;
+       case TGSI_OPCODE_IMIN:
+               op = LLVMIntSLT;
+               break;
+       case TGSI_OPCODE_UMAX:
+               op = LLVMIntUGT;
+               break;
+       case TGSI_OPCODE_UMIN:
+               op = LLVMIntULT;
+               break;
+       }
+
+       emit_data->output[emit_data->chan] =
+               LLVMBuildSelect(builder,
+                               LLVMBuildICmp(builder, op, emit_data->args[0],
+                                             emit_data->args[1], ""),
+                               emit_data->args[0],
+                               emit_data->args[1], "");
+}
+
 void radeon_llvm_context_init(struct radeon_llvm_context * ctx)
 {
        struct lp_type type;
@@ -1458,8 +1517,7 @@ void radeon_llvm_context_init(struct radeon_llvm_context * ctx)
        bld_base->op_actions[TGSI_OPCODE_CEIL].intr_name = "llvm.ceil.f32";
        bld_base->op_actions[TGSI_OPCODE_CLAMP].emit = build_tgsi_intrinsic_nomem;
        bld_base->op_actions[TGSI_OPCODE_CLAMP].intr_name = "llvm.AMDIL.clamp.";
-       bld_base->op_actions[TGSI_OPCODE_CMP].emit = build_tgsi_intrinsic_nomem;
-       bld_base->op_actions[TGSI_OPCODE_CMP].intr_name = "llvm.AMDGPU.cndlt";
+       bld_base->op_actions[TGSI_OPCODE_CMP].emit = emit_cmp;
        bld_base->op_actions[TGSI_OPCODE_CONT].emit = cont_emit;
        bld_base->op_actions[TGSI_OPCODE_COS].emit = build_tgsi_intrinsic_nomem;
        bld_base->op_actions[TGSI_OPCODE_COS].intr_name = "llvm.cos.f32";
@@ -1481,7 +1539,7 @@ void radeon_llvm_context_init(struct radeon_llvm_context * ctx)
        bld_base->op_actions[TGSI_OPCODE_ENDIF].emit = endif_emit;
        bld_base->op_actions[TGSI_OPCODE_ENDLOOP].emit = endloop_emit;
        bld_base->op_actions[TGSI_OPCODE_EX2].emit = build_tgsi_intrinsic_nomem;
-       bld_base->op_actions[TGSI_OPCODE_EX2].intr_name = "llvm.exp2.f32";
+       bld_base->op_actions[TGSI_OPCODE_EX2].intr_name = "llvm.AMDIL.exp.";
        bld_base->op_actions[TGSI_OPCODE_FLR].emit = build_tgsi_intrinsic_nomem;
        bld_base->op_actions[TGSI_OPCODE_FLR].intr_name = "llvm.floor.f32";
        bld_base->op_actions[TGSI_OPCODE_FMA].emit = build_tgsi_intrinsic_nomem;
@@ -1493,17 +1551,14 @@ void radeon_llvm_context_init(struct radeon_llvm_context * ctx)
        bld_base->op_actions[TGSI_OPCODE_FSGE].emit = emit_fcmp;
        bld_base->op_actions[TGSI_OPCODE_FSLT].emit = emit_fcmp;
        bld_base->op_actions[TGSI_OPCODE_FSNE].emit = emit_fcmp;
-       bld_base->op_actions[TGSI_OPCODE_IABS].emit = build_tgsi_intrinsic_nomem;
-       bld_base->op_actions[TGSI_OPCODE_IABS].intr_name = "llvm.AMDIL.abs.";
+       bld_base->op_actions[TGSI_OPCODE_IABS].emit = emit_iabs;
        bld_base->op_actions[TGSI_OPCODE_IBFE].emit = build_tgsi_intrinsic_nomem;
        bld_base->op_actions[TGSI_OPCODE_IBFE].intr_name = "llvm.AMDGPU.bfe.i32";
        bld_base->op_actions[TGSI_OPCODE_IDIV].emit = emit_idiv;
        bld_base->op_actions[TGSI_OPCODE_IF].emit = if_emit;
        bld_base->op_actions[TGSI_OPCODE_UIF].emit = uif_emit;
-       bld_base->op_actions[TGSI_OPCODE_IMAX].emit = build_tgsi_intrinsic_nomem;
-       bld_base->op_actions[TGSI_OPCODE_IMAX].intr_name = "llvm.AMDGPU.imax";
-       bld_base->op_actions[TGSI_OPCODE_IMIN].emit = build_tgsi_intrinsic_nomem;
-       bld_base->op_actions[TGSI_OPCODE_IMIN].intr_name = "llvm.AMDGPU.imin";
+       bld_base->op_actions[TGSI_OPCODE_IMAX].emit = emit_minmax_int;
+       bld_base->op_actions[TGSI_OPCODE_IMIN].emit = emit_minmax_int;
        bld_base->op_actions[TGSI_OPCODE_IMSB].emit = emit_imsb;
        bld_base->op_actions[TGSI_OPCODE_INEG].emit = emit_ineg;
        bld_base->op_actions[TGSI_OPCODE_ISHR].emit = emit_ishr;
@@ -1519,8 +1574,6 @@ void radeon_llvm_context_init(struct radeon_llvm_context * ctx)
        bld_base->op_actions[TGSI_OPCODE_LSB].emit = emit_lsb;
        bld_base->op_actions[TGSI_OPCODE_LG2].emit = build_tgsi_intrinsic_nomem;
        bld_base->op_actions[TGSI_OPCODE_LG2].intr_name = "llvm.log2.f32";
-       bld_base->op_actions[TGSI_OPCODE_LRP].emit = build_tgsi_intrinsic_nomem;
-       bld_base->op_actions[TGSI_OPCODE_LRP].intr_name = "llvm.AMDGPU.lrp";
        bld_base->op_actions[TGSI_OPCODE_MOD].emit = emit_mod;
        bld_base->op_actions[TGSI_OPCODE_UMSB].emit = emit_umsb;
        bld_base->op_actions[TGSI_OPCODE_NOT].emit = emit_not;
@@ -1533,13 +1586,13 @@ void radeon_llvm_context_init(struct radeon_llvm_context * ctx)
        bld_base->op_actions[TGSI_OPCODE_ROUND].intr_name = "llvm.rint.f32";
        bld_base->op_actions[TGSI_OPCODE_RSQ].intr_name = "llvm.AMDGPU.rsq.clamped.f32";
        bld_base->op_actions[TGSI_OPCODE_RSQ].emit = build_tgsi_intrinsic_nomem;
-       bld_base->op_actions[TGSI_OPCODE_SGE].emit = emit_cmp;
-       bld_base->op_actions[TGSI_OPCODE_SEQ].emit = emit_cmp;
+       bld_base->op_actions[TGSI_OPCODE_SGE].emit = emit_set_cond;
+       bld_base->op_actions[TGSI_OPCODE_SEQ].emit = emit_set_cond;
        bld_base->op_actions[TGSI_OPCODE_SHL].emit = emit_shl;
-       bld_base->op_actions[TGSI_OPCODE_SLE].emit = emit_cmp;
-       bld_base->op_actions[TGSI_OPCODE_SLT].emit = emit_cmp;
-       bld_base->op_actions[TGSI_OPCODE_SNE].emit = emit_cmp;
-       bld_base->op_actions[TGSI_OPCODE_SGT].emit = emit_cmp;
+       bld_base->op_actions[TGSI_OPCODE_SLE].emit = emit_set_cond;
+       bld_base->op_actions[TGSI_OPCODE_SLT].emit = emit_set_cond;
+       bld_base->op_actions[TGSI_OPCODE_SNE].emit = emit_set_cond;
+       bld_base->op_actions[TGSI_OPCODE_SGT].emit = emit_set_cond;
        bld_base->op_actions[TGSI_OPCODE_SIN].emit = build_tgsi_intrinsic_nomem;
        bld_base->op_actions[TGSI_OPCODE_SIN].intr_name = "llvm.sin.f32";
        bld_base->op_actions[TGSI_OPCODE_SQRT].emit = build_tgsi_intrinsic_nomem;
@@ -1551,10 +1604,8 @@ void radeon_llvm_context_init(struct radeon_llvm_context * ctx)
        bld_base->op_actions[TGSI_OPCODE_UBFE].emit = build_tgsi_intrinsic_nomem;
        bld_base->op_actions[TGSI_OPCODE_UBFE].intr_name = "llvm.AMDGPU.bfe.u32";
        bld_base->op_actions[TGSI_OPCODE_UDIV].emit = emit_udiv;
-       bld_base->op_actions[TGSI_OPCODE_UMAX].emit = build_tgsi_intrinsic_nomem;
-       bld_base->op_actions[TGSI_OPCODE_UMAX].intr_name = "llvm.AMDGPU.umax";
-       bld_base->op_actions[TGSI_OPCODE_UMIN].emit = build_tgsi_intrinsic_nomem;
-       bld_base->op_actions[TGSI_OPCODE_UMIN].intr_name = "llvm.AMDGPU.umin";
+       bld_base->op_actions[TGSI_OPCODE_UMAX].emit = emit_minmax_int;
+       bld_base->op_actions[TGSI_OPCODE_UMIN].emit = emit_minmax_int;
        bld_base->op_actions[TGSI_OPCODE_UMOD].emit = emit_umod;
        bld_base->op_actions[TGSI_OPCODE_USEQ].emit = emit_icmp;
        bld_base->op_actions[TGSI_OPCODE_USGE].emit = emit_icmp;