#define FB_BUFFER_OFFSET 0x1000
#define FB_BUFFER_SIZE 2048
+#define FB_BUFFER_SIZE_TONGA (2048 * 64)
#define IT_SCALING_TABLE_SIZE 992
+#define UVD_SESSION_CONTEXT_SIZE (128 * 1024)
/* UVD decoder representation */
struct ruvd_decoder {
struct rvid_buffer msg_fb_it_buffers[NUM_BUFFERS];
struct ruvd_msg *msg;
uint32_t *fb;
+ unsigned fb_size;
uint8_t *it;
struct rvid_buffer bs_buffers[NUM_BUFFERS];
struct rvid_buffer dpb;
bool use_legacy;
struct rvid_buffer ctx;
+ struct rvid_buffer sessionctx;
};
/* flush IB to the hardware */
-static void flush(struct ruvd_decoder *dec)
+static int flush(struct ruvd_decoder *dec, unsigned flags)
{
- dec->ws->cs_flush(dec->cs, RADEON_FLUSH_ASYNC, NULL);
+ return dec->ws->cs_flush(dec->cs, flags, NULL);
}
/* add a new set register command to the IB */
static void set_reg(struct ruvd_decoder *dec, unsigned reg, uint32_t val)
{
- uint32_t *pm4 = dec->cs->buf;
- pm4[dec->cs->cdw++] = RUVD_PKT0(reg >> 2, 0);
- pm4[dec->cs->cdw++] = val;
+ radeon_emit(dec->cs, RUVD_PKT0(reg >> 2, 0));
+ radeon_emit(dec->cs, val);
}
/* send a command to the VCPU through the GPCOM registers */
{
int reloc_idx;
- reloc_idx = dec->ws->cs_add_buffer(dec->cs, buf, usage, domain,
+ reloc_idx = dec->ws->cs_add_buffer(dec->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED,
+ domain,
RADEON_PRIO_UVD);
if (!dec->use_legacy) {
uint64_t addr;
set_reg(dec, RUVD_GPCOM_VCPU_DATA0, addr);
set_reg(dec, RUVD_GPCOM_VCPU_DATA1, addr >> 32);
} else {
+ off += dec->ws->buffer_get_reloc_offset(buf);
set_reg(dec, RUVD_GPCOM_VCPU_DATA0, off);
set_reg(dec, RUVD_GPCOM_VCPU_DATA1, reloc_idx * 4);
}
dec->msg = (struct ruvd_msg *)ptr;
dec->fb = (uint32_t *)(ptr + FB_BUFFER_OFFSET);
if (have_it(dec))
- dec->it = (uint8_t *)(ptr + FB_BUFFER_OFFSET + FB_BUFFER_SIZE);
+ dec->it = (uint8_t *)(ptr + FB_BUFFER_OFFSET + dec->fb_size);
}
/* unmap and send a message command to the VCPU */
dec->fb = NULL;
dec->it = NULL;
+
+ if (dec->sessionctx.res)
+ send_cmd(dec, RUVD_CMD_SESSION_CONTEXT_BUFFER,
+ dec->sessionctx.res->buf, 0, RADEON_USAGE_READWRITE,
+ RADEON_DOMAIN_VRAM);
+
/* and send it to the hardware */
send_cmd(dec, RUVD_CMD_MSG_BUFFER, buf->res->buf, 0,
RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
}
}
+static unsigned calc_ctx_size_h264_perf(struct ruvd_decoder *dec)
+{
+ unsigned width_in_mb, height_in_mb, ctx_size;
+ unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
+ unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
+
+ unsigned max_references = dec->base.max_references + 1;
+
+ // picture width & height in 16 pixel units
+ width_in_mb = width / VL_MACROBLOCK_WIDTH;
+ height_in_mb = align(height / VL_MACROBLOCK_HEIGHT, 2);
+
+ if (!dec->use_legacy) {
+ unsigned fs_in_mb = width_in_mb * height_in_mb;
+ unsigned num_dpb_buffer;
+ switch(dec->base.level) {
+ case 30:
+ num_dpb_buffer = 8100 / fs_in_mb;
+ break;
+ case 31:
+ num_dpb_buffer = 18000 / fs_in_mb;
+ break;
+ case 32:
+ num_dpb_buffer = 20480 / fs_in_mb;
+ break;
+ case 41:
+ num_dpb_buffer = 32768 / fs_in_mb;
+ break;
+ case 42:
+ num_dpb_buffer = 34816 / fs_in_mb;
+ break;
+ case 50:
+ num_dpb_buffer = 110400 / fs_in_mb;
+ break;
+ case 51:
+ num_dpb_buffer = 184320 / fs_in_mb;
+ break;
+ default:
+ num_dpb_buffer = 184320 / fs_in_mb;
+ break;
+ }
+ num_dpb_buffer++;
+ max_references = MAX2(MIN2(NUM_H264_REFS, num_dpb_buffer), max_references);
+ ctx_size = max_references * align(width_in_mb * height_in_mb * 192, 256);
+ } else {
+ // the firmware seems to always assume a minimum of ref frames
+ max_references = MAX2(NUM_H264_REFS, max_references);
+ // macroblock context buffer
+ ctx_size = align(width_in_mb * height_in_mb * max_references * 192, 256);
+ }
+
+ return ctx_size;
+}
+
static unsigned calc_ctx_size_h265_main(struct ruvd_decoder *dec)
{
unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
num_dpb_buffer++;
max_references = MAX2(MIN2(NUM_H264_REFS, num_dpb_buffer), max_references);
dpb_size = image_size * max_references;
- dpb_size += max_references * align(width_in_mb * height_in_mb * 192, alignment);
- dpb_size += align(width_in_mb * height_in_mb * 32, alignment);
+ if ((dec->stream_type != RUVD_CODEC_H264_PERF) ||
+ (((struct r600_common_screen*)dec->screen)->family < CHIP_POLARIS10)) {
+ dpb_size += max_references * align(width_in_mb * height_in_mb * 192, alignment);
+ dpb_size += align(width_in_mb * height_in_mb * 32, alignment);
+ }
} else {
// the firmware seems to allways assume a minimum of ref frames
max_references = MAX2(NUM_H264_REFS, max_references);
// reference picture buffer
dpb_size = image_size * max_references;
- // macroblock context buffer
- dpb_size += width_in_mb * height_in_mb * max_references * 192;
- // IT surface buffer
- dpb_size += width_in_mb * height_in_mb * 32;
+ if ((dec->stream_type != RUVD_CODEC_H264_PERF) ||
+ (((struct r600_common_screen*)dec->screen)->family < CHIP_POLARIS10)) {
+ // macroblock context buffer
+ dpb_size += width_in_mb * height_in_mb * max_references * 192;
+ // IT surface buffer
+ dpb_size += width_in_mb * height_in_mb * 32;
+ }
}
break;
}
dec->msg->stream_handle = dec->stream_handle;
send_msg_buf(dec);
- flush(dec);
+ flush(dec, 0);
dec->ws->cs_destroy(dec->cs);
}
rvid_destroy_buffer(&dec->dpb);
- if (u_reduce_video_profile(dec->base.profile) == PIPE_VIDEO_FORMAT_HEVC)
- rvid_destroy_buffer(&dec->ctx);
+ rvid_destroy_buffer(&dec->ctx);
+ rvid_destroy_buffer(&dec->sessionctx);
FREE(dec);
}
dec->msg->body.decode.bsd_size = bs_size;
dec->msg->body.decode.db_pitch = align(dec->base.width, 16);
+ if (dec->stream_type == RUVD_CODEC_H264_PERF &&
+ ((struct r600_common_screen*)dec->screen)->family >= CHIP_POLARIS10)
+ dec->msg->body.decode.dpb_reserved = dec->ctx.res->buf->size;
+
dt = dec->set_dtb(dec->msg, (struct vl_video_buffer *)target);
if (((struct r600_common_screen*)dec->screen)->family >= CHIP_STONEY)
dec->msg->body.decode.dt_wa_chroma_top_offset = dec->msg->body.decode.dt_pitch / 2;
}
rvid_clear_buffer(decoder->context, &dec->ctx);
}
+
+ if (dec->ctx.res)
+ dec->msg->body.decode.dpb_reserved = dec->ctx.res->buf->size;
break;
case PIPE_VIDEO_FORMAT_VC1:
dec->msg->body.decode.extension_support = 0x1;
/* set at least the feedback buffer size */
- dec->fb[0] = FB_BUFFER_SIZE;
+ dec->fb[0] = dec->fb_size;
send_msg_buf(dec);
send_cmd(dec, RUVD_CMD_DPB_BUFFER, dec->dpb.res->buf, 0,
RADEON_USAGE_READWRITE, RADEON_DOMAIN_VRAM);
- if (u_reduce_video_profile(picture->profile) == PIPE_VIDEO_FORMAT_HEVC) {
+ if (dec->ctx.res)
send_cmd(dec, RUVD_CMD_CONTEXT_BUFFER, dec->ctx.res->buf, 0,
RADEON_USAGE_READWRITE, RADEON_DOMAIN_VRAM);
- }
send_cmd(dec, RUVD_CMD_BITSTREAM_BUFFER, bs_buf->res->buf,
0, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
send_cmd(dec, RUVD_CMD_DECODING_TARGET_BUFFER, dt, 0,
FB_BUFFER_OFFSET, RADEON_USAGE_WRITE, RADEON_DOMAIN_GTT);
if (have_it(dec))
send_cmd(dec, RUVD_CMD_ITSCALING_TABLE_BUFFER, msg_fb_it_buf->res->buf,
- FB_BUFFER_OFFSET + FB_BUFFER_SIZE, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
+ FB_BUFFER_OFFSET + dec->fb_size, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
set_reg(dec, RUVD_ENGINE_CNTL, 1);
- flush(dec);
+ flush(dec, RADEON_FLUSH_ASYNC);
next_buffer(dec);
}
unsigned bs_buf_size;
struct radeon_info info;
struct ruvd_decoder *dec;
- int i;
+ int r, i;
ws->query_info(ws, &info);
/* fall through */
case PIPE_VIDEO_FORMAT_MPEG4:
+ width = align(width, VL_MACROBLOCK_WIDTH);
+ height = align(height, VL_MACROBLOCK_HEIGHT);
+ break;
case PIPE_VIDEO_FORMAT_MPEG4_AVC:
width = align(width, VL_MACROBLOCK_WIDTH);
height = align(height, VL_MACROBLOCK_HEIGHT);
return NULL;
if (info.drm_major < 3)
- dec->use_legacy = TRUE;
+ dec->use_legacy = true;
dec->base = *templ;
dec->base.context = context;
goto error;
}
- bs_buf_size = width * height * 512 / (16 * 16);
+ dec->fb_size = (info.family == CHIP_TONGA) ? FB_BUFFER_SIZE_TONGA :
+ FB_BUFFER_SIZE;
+ bs_buf_size = width * height * (512 / (16 * 16));
for (i = 0; i < NUM_BUFFERS; ++i) {
- unsigned msg_fb_it_size = FB_BUFFER_OFFSET + FB_BUFFER_SIZE;
+ unsigned msg_fb_it_size = FB_BUFFER_OFFSET + dec->fb_size;
STATIC_ASSERT(sizeof(struct ruvd_msg) <= FB_BUFFER_OFFSET);
if (have_it(dec))
msg_fb_it_size += IT_SCALING_TABLE_SIZE;
rvid_clear_buffer(context, &dec->dpb);
+ if (dec->stream_type == RUVD_CODEC_H264_PERF && info.family >= CHIP_POLARIS10) {
+ unsigned ctx_size = calc_ctx_size_h264_perf(dec);
+ if (!rvid_create_buffer(dec->screen, &dec->ctx, ctx_size, PIPE_USAGE_DEFAULT)) {
+ RVID_ERR("Can't allocated context buffer.\n");
+ goto error;
+ }
+ rvid_clear_buffer(context, &dec->ctx);
+ }
+
+ if (info.family >= CHIP_POLARIS10 && info.drm_minor >= 3) {
+ if (!rvid_create_buffer(dec->screen, &dec->sessionctx,
+ UVD_SESSION_CONTEXT_SIZE,
+ PIPE_USAGE_DEFAULT)) {
+ RVID_ERR("Can't allocated session ctx.\n");
+ goto error;
+ }
+ rvid_clear_buffer(context, &dec->sessionctx);
+ }
+
map_msg_fb_it_buf(dec);
dec->msg->size = sizeof(*dec->msg);
dec->msg->msg_type = RUVD_MSG_CREATE;
dec->msg->body.create.height_in_samples = dec->base.height;
dec->msg->body.create.dpb_size = dpb_size;
send_msg_buf(dec);
- flush(dec);
+ r = flush(dec, 0);
+ if (r)
+ goto error;
+
next_buffer(dec);
return &dec->base;
}
rvid_destroy_buffer(&dec->dpb);
- if (u_reduce_video_profile(dec->base.profile) == PIPE_VIDEO_FORMAT_HEVC)
- rvid_destroy_buffer(&dec->ctx);
+ rvid_destroy_buffer(&dec->ctx);
+ rvid_destroy_buffer(&dec->sessionctx);
FREE(dec);
void ruvd_set_dt_surfaces(struct ruvd_msg *msg, struct radeon_surf *luma,
struct radeon_surf *chroma)
{
- msg->body.decode.dt_pitch = luma->level[0].pitch_bytes;
+ msg->body.decode.dt_pitch = luma->level[0].nblk_x * luma->bpe;
switch (luma->level[0].mode) {
case RADEON_SURF_MODE_LINEAR_ALIGNED:
msg->body.decode.dt_tiling_mode = RUVD_TILE_LINEAR;
projects / mesa.git / blobdiff