ruvd_set_dtb set_dtb)
{
unsigned dpb_size = calc_dpb_size(profile, width, height, max_references);
+ struct radeon_info info;
struct ruvd_decoder *dec;
struct ruvd_msg msg;
int i;
+ ws->query_info(ws, &info);
+
switch(u_reduce_video_profile(profile)) {
case PIPE_VIDEO_CODEC_MPEG12:
- if (entrypoint > PIPE_VIDEO_ENTRYPOINT_BITSTREAM)
+ if (entrypoint > PIPE_VIDEO_ENTRYPOINT_BITSTREAM || info.family < CHIP_PALM)
return vl_create_mpeg12_decoder(context, profile, entrypoint,
chroma_format, width,
height, max_references, expect_chunked_decode);
return true;
case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
return true;
+ case PIPE_VIDEO_CAP_MAX_LEVEL:
+ switch (profile) {
+ case PIPE_VIDEO_PROFILE_MPEG1:
+ return 0;
+ case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
+ case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
+ return 3;
+ case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
+ return 3;
+ case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
+ return 5;
+ case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
+ return 1;
+ case PIPE_VIDEO_PROFILE_VC1_MAIN:
+ return 2;
+ case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
+ return 4;
+ case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
+ case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
+ case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
+ return 41;
+ default:
+ return 0;
+ }
default:
return 0;
}