st/va: add BOB deinterlacing v2

[mesa.git] / src / gallium / drivers / radeon / radeon_uvd.h

diff --git a/src/gallium/drivers/radeon/radeon_uvd.h b/src/gallium/drivers/radeon/radeon_uvd.h
index 7442865c9ec4ef2be2871de5dbaa75d825be7061..30738bf0e82c82a095920745b29d9cf74390537d 100644 (file)
--- a/src/gallium/drivers/radeon/radeon_uvd.h
+++ b/src/gallium/drivers/radeon/radeon_uvd.h
@@ -62,6 +62,8 @@
 #define RUVD_CMD_DECODING_TARGET_BUFFER        0x00000002
 #define RUVD_CMD_FEEDBACK_BUFFER       0x00000003
 #define RUVD_CMD_BITSTREAM_BUFFER      0x00000100
+#define RUVD_CMD_ITSCALING_TABLE_BUFFER        0x00000204
+#define RUVD_CMD_CONTEXT_BUFFER                0x00000206
 
 /* UVD message types */
 #define RUVD_MSG_CREATE                0
@@ -73,6 +75,8 @@
 #define RUVD_CODEC_VC1         0x00000001
 #define RUVD_CODEC_MPEG2       0x00000003
 #define RUVD_CODEC_MPEG4       0x00000004
+#define RUVD_CODEC_H264_PERF   0x00000007
+#define RUVD_CODEC_H265                0x00000010
 
 /* UVD decode target buffer tiling mode */
 #define RUVD_TILE_LINEAR       0x00000000
@@ -171,6 +175,75 @@ struct ruvd_h264 {
        } mvc;
 };
 
+struct ruvd_h265 {
+       uint32_t        sps_info_flags;
+       uint32_t        pps_info_flags;
+
+       uint8_t         chroma_format;
+       uint8_t         bit_depth_luma_minus8;
+       uint8_t         bit_depth_chroma_minus8;
+       uint8_t         log2_max_pic_order_cnt_lsb_minus4;
+
+       uint8_t         sps_max_dec_pic_buffering_minus1;
+       uint8_t         log2_min_luma_coding_block_size_minus3;
+       uint8_t         log2_diff_max_min_luma_coding_block_size;
+       uint8_t         log2_min_transform_block_size_minus2;
+
+       uint8_t         log2_diff_max_min_transform_block_size;
+       uint8_t         max_transform_hierarchy_depth_inter;
+       uint8_t         max_transform_hierarchy_depth_intra;
+       uint8_t         pcm_sample_bit_depth_luma_minus1;
+
+       uint8_t         pcm_sample_bit_depth_chroma_minus1;
+       uint8_t         log2_min_pcm_luma_coding_block_size_minus3;
+       uint8_t         log2_diff_max_min_pcm_luma_coding_block_size;
+       uint8_t         num_extra_slice_header_bits;
+
+       uint8_t         num_short_term_ref_pic_sets;
+       uint8_t         num_long_term_ref_pic_sps;
+       uint8_t         num_ref_idx_l0_default_active_minus1;
+       uint8_t         num_ref_idx_l1_default_active_minus1;
+
+       int8_t          pps_cb_qp_offset;
+       int8_t          pps_cr_qp_offset;
+       int8_t          pps_beta_offset_div2;
+       int8_t          pps_tc_offset_div2;
+
+       uint8_t         diff_cu_qp_delta_depth;
+       uint8_t         num_tile_columns_minus1;
+       uint8_t         num_tile_rows_minus1;
+       uint8_t         log2_parallel_merge_level_minus2;
+
+       uint16_t        column_width_minus1[19];
+       uint16_t        row_height_minus1[21];
+
+       int8_t          init_qp_minus26;
+       uint8_t         num_delta_pocs_ref_rps_idx;
+       uint8_t         curr_idx;
+       uint8_t         reserved1;
+       int32_t         curr_poc;
+       uint8_t         ref_pic_list[16];
+       int32_t         poc_list[16];
+       uint8_t         ref_pic_set_st_curr_before[8];
+       uint8_t         ref_pic_set_st_curr_after[8];
+       uint8_t         ref_pic_set_lt_curr[8];
+
+       uint8_t         ucScalingListDCCoefSizeID2[6];
+       uint8_t         ucScalingListDCCoefSizeID3[2];
+
+       uint8_t         highestTid;
+       uint8_t         isNonRef;
+
+       uint8_t         p010_mode;
+       uint8_t         msb_mode;
+       uint8_t         luma_10to8;
+       uint8_t         chroma_10to8;
+       uint8_t         sclr_luma10to8;
+       uint8_t         sclr_chroma10to8;
+
+       uint8_t         direct_reflist[2][15];
+};
+
 struct ruvd_vc1 {
        uint32_t        profile;
        uint32_t        level;
@@ -321,12 +394,16 @@ struct ruvd_msg {
                        uint32_t        dt_chroma_top_offset;
                        uint32_t        dt_chroma_bottom_offset;
                        uint32_t        dt_surf_tile_config;
-                       uint32_t        dt_reserved[3];
+                       uint32_t        dt_uv_surf_tile_config;
+                       // re-use dt_wa_chroma_top_offset as dt_ext_info for UV pitch in stoney
+                       uint32_t        dt_wa_chroma_top_offset;
+                       uint32_t        dt_wa_chroma_bottom_offset;
 
                        uint32_t        reserved[16];
 
                        union {
                                struct ruvd_h264        h264;
+                               struct ruvd_h265        h265;
                                struct ruvd_vc1         vc1;
                                struct ruvd_mpeg2       mpeg2;
                                struct ruvd_mpeg4       mpeg4;
@@ -344,7 +421,7 @@ struct ruvd_msg {
 };
 
 /* driver dependent callback */
-typedef struct radeon_winsys_cs_handle* (*ruvd_set_dtb)
+typedef struct pb_buffer* (*ruvd_set_dtb)
 (struct ruvd_msg* msg, struct vl_video_buffer *vb);
 
 /* create an UVD decode */