gallium/u_blitter: use draw_rectangle callback for layered clears

[mesa.git] / src / gallium / drivers / radeon / radeon_uvd.h

diff --git a/src/gallium/drivers/radeon/radeon_uvd.h b/src/gallium/drivers/radeon/radeon_uvd.h
index 88013bd56535ed348e4fd4c99b2a981b64ab03e4..a927c843dac4cc1d41bb95dcb1f8d9d48dbb83e8 100644 (file)
--- a/src/gallium/drivers/radeon/radeon_uvd.h
+++ b/src/gallium/drivers/radeon/radeon_uvd.h
@@ -38,13 +38,13 @@
 #include "vl/vl_video_buffer.h"
 
 /* UVD uses PM4 packet type 0 and 2 */
-#define RUVD_PKT_TYPE_S(x)             (((x) & 0x3) << 30)
+#define RUVD_PKT_TYPE_S(x)             (((unsigned)(x) & 0x3) << 30)
 #define RUVD_PKT_TYPE_G(x)             (((x) >> 30) & 0x3)
 #define RUVD_PKT_TYPE_C                        0x3FFFFFFF
-#define RUVD_PKT_COUNT_S(x)            (((x) & 0x3FFF) << 16)
+#define RUVD_PKT_COUNT_S(x)            (((unsigned)(x) & 0x3FFF) << 16)
 #define RUVD_PKT_COUNT_G(x)            (((x) >> 16) & 0x3FFF)
 #define RUVD_PKT_COUNT_C               0xC000FFFF
-#define RUVD_PKT0_BASE_INDEX_S(x)      (((x) & 0xFFFF) << 0)
+#define RUVD_PKT0_BASE_INDEX_S(x)      (((unsigned)(x) & 0xFFFF) << 0)
 #define RUVD_PKT0_BASE_INDEX_G(x)      (((x) >> 0) & 0xFFFF)
 #define RUVD_PKT0_BASE_INDEX_C         0xFFFF0000
 #define RUVD_PKT0(index, count)                (RUVD_PKT_TYPE_S(0) | RUVD_PKT0_BASE_INDEX_S(index) | RUVD_PKT_COUNT_S(count))
@@ -56,11 +56,17 @@
 #define RUVD_GPCOM_VCPU_DATA1          0xEF14
 #define RUVD_ENGINE_CNTL               0xEF18
 
+#define RUVD_GPCOM_VCPU_CMD_SOC15              0x2070c
+#define RUVD_GPCOM_VCPU_DATA0_SOC15            0x20710
+#define RUVD_GPCOM_VCPU_DATA1_SOC15            0x20714
+#define RUVD_ENGINE_CNTL_SOC15                 0x20718
+
 /* UVD commands to VCPU */
 #define RUVD_CMD_MSG_BUFFER            0x00000000
 #define RUVD_CMD_DPB_BUFFER            0x00000001
 #define RUVD_CMD_DECODING_TARGET_BUFFER        0x00000002
 #define RUVD_CMD_FEEDBACK_BUFFER       0x00000003
+#define RUVD_CMD_SESSION_CONTEXT_BUFFER        0x00000005
 #define RUVD_CMD_BITSTREAM_BUFFER      0x00000100
 #define RUVD_CMD_ITSCALING_TABLE_BUFFER        0x00000204
 #define RUVD_CMD_CONTEXT_BUFFER                0x00000206
@@ -76,6 +82,7 @@
 #define RUVD_CODEC_MPEG2       0x00000003
 #define RUVD_CODEC_MPEG4       0x00000004
 #define RUVD_CODEC_H264_PERF   0x00000007
+#define RUVD_CODEC_MJPEG       0x00000008
 #define RUVD_CODEC_H265                0x00000010
 
 /* UVD decode target buffer tiling mode */
@@ -110,6 +117,11 @@
 #define RUVD_VC1_PROFILE_MAIN          0x00000001
 #define RUVD_VC1_PROFILE_ADVANCED      0x00000002
 
+enum ruvd_surface_type {
+       RUVD_SURFACE_TYPE_LEGACY = 0,
+       RUVD_SURFACE_TYPE_GFX9
+};
+
 struct ruvd_mvc_element {
        uint16_t        viewOrderIndex;
        uint16_t        viewId;
@@ -421,7 +433,7 @@ struct ruvd_msg {
 };
 
 /* driver dependent callback */
-typedef struct radeon_winsys_cs_handle* (*ruvd_set_dtb)
+typedef struct pb_buffer* (*ruvd_set_dtb)
 (struct ruvd_msg* msg, struct vl_video_buffer *vb);
 
 /* create an UVD decode */
@@ -431,5 +443,5 @@ struct pipe_video_codec *ruvd_create_decoder(struct pipe_context *context,
 
 /* fill decoding target field from the luma and chroma surfaces */
 void ruvd_set_dt_surfaces(struct ruvd_msg *msg, struct radeon_surf *luma,
-                         struct radeon_surf *chroma);
+                       struct radeon_surf *chroma, enum ruvd_surface_type type);
 #endif