svga: s/0/FALSE/

[mesa.git] / src / gallium / drivers / radeon / radeon_uvd.h

diff --git a/src/gallium/drivers/radeon/radeon_uvd.h b/src/gallium/drivers/radeon/radeon_uvd.h
index 82fbda4d1ee55b06b3be10300921f9b1bfe242da..b0135bac5d7ef60c09b88ccd473227da1c318492 100644 (file)
--- a/src/gallium/drivers/radeon/radeon_uvd.h
+++ b/src/gallium/drivers/radeon/radeon_uvd.h
@@ -345,10 +345,9 @@ typedef struct radeon_winsys_cs_handle* (*ruvd_set_dtb)
 (struct ruvd_msg* msg, struct vl_video_buffer *vb);
 
 /* create an UVD decode */
-struct pipe_video_decoder *ruvd_create_decoder(struct pipe_context *context,
-                                              const struct pipe_video_decoder *templat,
-                                              struct radeon_winsys* ws,
-                                              ruvd_set_dtb set_dtb);
+struct pipe_video_codec *ruvd_create_decoder(struct pipe_context *context,
+                                            const struct pipe_video_codec *templat,
+                                            ruvd_set_dtb set_dtb);
 
 /* join surfaces into the same buffer with identical tiling params
    sumup their sizes and replace the backend buffers with a single bo */
@@ -363,11 +362,13 @@ void ruvd_set_dt_surfaces(struct ruvd_msg *msg, struct radeon_surface *luma,
 /* returns supported codecs and other parameters */
 int ruvd_get_video_param(struct pipe_screen *screen,
                         enum pipe_video_profile profile,
+                        enum pipe_video_entrypoint entrypoint,
                         enum pipe_video_cap param);
 
 /* the hardware only supports NV12 */
 boolean ruvd_is_format_supported(struct pipe_screen *screen,
                                 enum pipe_format format,
-                                enum pipe_video_profile profile);
+                                enum pipe_video_profile profile,
+                                enum pipe_video_entrypoint entrypoint);
 
 #endif