lima/gpir: Always schedule complex2 and *_impl right after complex1

[mesa.git] / src / gallium / drivers / radeon / radeon_uvd_enc_1_1.c

diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
index 42a9fa9abf0591ecadfe2e9a3e6c62e35a1fb396..7e5be33ec54b8740b2c0b1783ce6b633ade5a544 100644 (file)
--- a/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
@@ -55,7 +55,7 @@ radeon_uvd_enc_add_buffer(struct radeon_uvd_encoder *enc,
                           enum radeon_bo_domain domain, signed offset)
 {
    enc->ws->cs_add_buffer(enc->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED,
-                          domain, RADEON_PRIO_VCE);
+                          domain, 0);
    uint64_t addr;
    addr = enc->ws->buffer_get_virtual_address(buf);
    addr = addr + offset;
@@ -573,7 +573,13 @@ radeon_uvd_enc_nalu_pps_hevc(struct radeon_uvd_encoder *enc)
                                   enc->enc_pic.hevc_spec_misc.
                                   constrained_intra_pred_flag, 1);
    radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
-   radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
+   if (enc->enc_pic.rc_session_init.rate_control_method ==
+      RENC_UVD_RATE_CONTROL_METHOD_NONE)
+      radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
+   else {
+      radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
+      radeon_uvd_enc_code_ue(enc, 0x0);
+   }
    radeon_uvd_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);
    radeon_uvd_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);
    radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
@@ -768,8 +774,7 @@ radeon_uvd_enc_slice_header_hevc(struct radeon_uvd_encoder *enc)
    if ((enc->enc_pic.nal_unit_type != 19)
        && (enc->enc_pic.nal_unit_type != 20)) {
       radeon_uvd_enc_code_fixed_bits(enc,
-                                     enc->enc_pic.frame_num %
-                                     enc->enc_pic.max_poc,
+                                     enc->enc_pic.pic_order_cnt,
                                      enc->enc_pic.log2_max_poc);
       if (enc->enc_pic.picture_type == PIPE_H265_ENC_PICTURE_TYPE_P)
          radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
@@ -835,10 +840,10 @@ radeon_uvd_enc_slice_header_hevc(struct radeon_uvd_encoder *enc)
 static void
 radeon_uvd_enc_ctx(struct radeon_uvd_encoder *enc)
 {
-   struct si_screen *rscreen = (struct si_screen *) enc->screen;
+   struct si_screen *sscreen = (struct si_screen *) enc->screen;
 
    enc->enc_pic.ctx_buf.swizzle_mode = 0;
-   if (rscreen->info.chip_class < GFX9) {
+   if (sscreen->info.chip_class < GFX9) {
       enc->enc_pic.ctx_buf.rec_luma_pitch =
          (enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe);
       enc->enc_pic.ctx_buf.rec_chroma_pitch =
@@ -950,7 +955,7 @@ radeon_uvd_enc_rc_per_pic(struct radeon_uvd_encoder *enc,
 static void
 radeon_uvd_enc_encode_params_hevc(struct radeon_uvd_encoder *enc)
 {
-   struct si_screen *rscreen = (struct si_screen *) enc->screen;
+   struct si_screen *sscreen = (struct si_screen *) enc->screen;
    switch (enc->enc_pic.picture_type) {
    case PIPE_H265_ENC_PICTURE_TYPE_I:
    case PIPE_H265_ENC_PICTURE_TYPE_IDR:
@@ -970,7 +975,7 @@ radeon_uvd_enc_encode_params_hevc(struct radeon_uvd_encoder *enc)
    }
 
    enc->enc_pic.enc_params.allowed_max_bitstream_size = enc->bs_size;
-   if (rscreen->info.chip_class < GFX9) {
+   if (sscreen->info.chip_class < GFX9) {
       enc->enc_pic.enc_params.input_pic_luma_pitch =
          (enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe);
       enc->enc_pic.enc_params.input_pic_chroma_pitch =
@@ -998,7 +1003,7 @@ radeon_uvd_enc_encode_params_hevc(struct radeon_uvd_encoder *enc)
    RADEON_ENC_CS(enc->enc_pic.enc_params.pic_type);
    RADEON_ENC_CS(enc->enc_pic.enc_params.allowed_max_bitstream_size);
 
-   if (rscreen->info.chip_class < GFX9) {
+   if (sscreen->info.chip_class < GFX9) {
       RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM,
                       enc->luma->u.legacy.level[0].offset);
       RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM,