#define FW_52_8_3 ((52 << 24) | (8 << 16) | (3 << 8))
#define FW_53 (53 << 24)
+/* version specific function for getting parameters */
+static void (*si_get_pic_param)(struct rvce_encoder *enc,
+ struct pipe_h264_enc_picture_desc *pic) = NULL;
+
/**
* flush commands to the hardware
*/
{
unsigned i;
- LIST_INITHEAD(&enc->cpb_slots);
+ list_inithead(&enc->cpb_slots);
for (i = 0; i < enc->cpb_num; ++i) {
struct rvce_cpb_slot *slot = &enc->cpb_array[i];
slot->index = i;
slot->picture_type = PIPE_H264_ENC_PICTURE_TYPE_SKIP;
slot->frame_num = 0;
slot->pic_order_cnt = 0;
- LIST_ADDTAIL(&slot->list, &enc->cpb_slots);
+ list_addtail(&slot->list, &enc->cpb_slots);
}
}
}
if (l1) {
- LIST_DEL(&l1->list);
- LIST_ADD(&l1->list, &enc->cpb_slots);
+ list_del(&l1->list);
+ list_add(&l1->list, &enc->cpb_slots);
}
if (l0) {
- LIST_DEL(&l0->list);
- LIST_ADD(&l0->list, &enc->cpb_slots);
+ list_del(&l0->list);
+ list_add(&l0->list, &enc->cpb_slots);
}
}
enc->fb = &fb;
enc->session(enc);
enc->destroy(enc);
- enc->feedback(enc);
flush(enc);
si_vid_destroy_buffer(&fb);
}
slot->frame_num = enc->pic.frame_num;
slot->pic_order_cnt = enc->pic.pic_order_cnt;
if (!enc->pic.not_referenced) {
- LIST_DEL(&slot->list);
- LIST_ADD(&slot->list, &enc->cpb_slots);
+ list_del(&slot->list);
+ list_add(&slot->list, &enc->cpb_slots);
}
}
struct rvid_buffer *fb = feedback;
if (size) {
- uint32_t *ptr = enc->ws->buffer_map(fb->res->buf, enc->cs, PIPE_TRANSFER_READ_WRITE);
+ uint32_t *ptr = enc->ws->buffer_map(
+ fb->res->buf, enc->cs,
+ PIPE_TRANSFER_READ_WRITE | RADEON_TRANSFER_TEMPORARY);
if (ptr[1]) {
*size = ptr[4] - ptr[9];
rvce_get_buffer get_buffer)
{
struct si_screen *sscreen = (struct si_screen *)context->screen;
- struct r600_common_context *rctx = (struct r600_common_context*)context;
+ struct si_context *sctx = (struct si_context*)context;
struct rvce_encoder *enc;
struct pipe_video_buffer *tmp_buf, templat = {};
struct radeon_surf *tmp_surf;
if (!enc)
return NULL;
- if (sscreen->info.drm_major == 3)
+ if (sscreen->info.is_amdgpu)
enc->use_vm = true;
- if ((sscreen->info.drm_major == 2 && sscreen->info.drm_minor >= 42) ||
- sscreen->info.drm_major == 3)
+ if ((!sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 42) ||
+ sscreen->info.is_amdgpu)
enc->use_vui = true;
if (sscreen->info.family >= CHIP_TONGA &&
sscreen->info.family != CHIP_STONEY &&
sscreen->info.family != CHIP_POLARIS11 &&
- sscreen->info.family != CHIP_POLARIS12)
+ sscreen->info.family != CHIP_POLARIS12 &&
+ sscreen->info.family != CHIP_VEGAM)
enc->dual_pipe = true;
/* TODO enable B frame with dual instance */
if ((sscreen->info.family >= CHIP_TONGA) &&
enc->screen = context->screen;
enc->ws = ws;
- enc->cs = ws->cs_create(rctx->ctx, RING_VCE, rvce_cs_flush, enc);
+ enc->cs = ws->cs_create(sctx->ctx, RING_VCE, rvce_cs_flush, enc, false);
if (!enc->cs) {
RVID_ERR("Can't get command submission context.\n");
goto error;
break;
default:
- if ((sscreen->info.vce_fw_version & (0xff << 24)) == FW_53) {
+ if ((sscreen->info.vce_fw_version & (0xff << 24)) >= FW_53) {
si_vce_52_init(enc);
si_get_pic_param = si_vce_52_get_param;
} else
case FW_52_8_3:
return true;
default:
- if ((sscreen->info.vce_fw_version & (0xff << 24)) == FW_53)
+ if ((sscreen->info.vce_fw_version & (0xff << 24)) >= FW_53)
return true;
else
return false;
int reloc_idx;
reloc_idx = enc->ws->cs_add_buffer(enc->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED,
- domain, RADEON_PRIO_VCE);
+ domain, 0);
if (enc->use_vm) {
uint64_t addr;
addr = enc->ws->buffer_get_virtual_address(buf);