#define FW_40_2_2 ((40 << 24) | (2 << 16) | (2 << 8))
#define FW_50_0_1 ((50 << 24) | (0 << 16) | (1 << 8))
#define FW_50_1_2 ((50 << 24) | (1 << 16) | (2 << 8))
+#define FW_50_10_2 ((50 << 24) | (10 << 16) | (2 << 8))
+#define FW_50_17_3 ((50 << 24) | (17 << 16) | (3 << 8))
+#define FW_52_0_3 ((52 << 24) | (0 << 16) | (3 << 8))
/**
* flush commands to the hardware
static void flush(struct rvce_encoder *enc)
{
enc->ws->cs_flush(enc->cs, RADEON_FLUSH_ASYNC, NULL, 0);
+ enc->task_info_idx = 0;
+ enc->bs_idx = 0;
}
#if 0
* Calculate the offsets into the CPB
*/
void rvce_frame_offset(struct rvce_encoder *enc, struct rvce_cpb_slot *slot,
- unsigned *luma_offset, unsigned *chroma_offset)
+ signed *luma_offset, signed *chroma_offset)
{
unsigned pitch = align(enc->luma->level[0].pitch_bytes, 128);
unsigned vpitch = align(enc->luma->npix_y, 16);
enc->fb = &fb;
enc->session(enc);
enc->create(enc);
- enc->rate_control(enc);
- need_rate_control = false;
- enc->config_extension(enc);
- enc->motion_estimation(enc);
- enc->rdo(enc);
- if (enc->use_vui)
- enc->vui(enc);
- enc->pic_control(enc);
+ enc->config(enc);
enc->feedback(enc);
flush(enc);
//dump_feedback(enc, &fb);
rvid_destroy_buffer(&fb);
+ need_rate_control = false;
}
- enc->session(enc);
-
- if (need_rate_control)
- enc->rate_control(enc);
+ if (need_rate_control) {
+ enc->session(enc);
+ enc->config(enc);
+ flush(enc);
+ }
}
static void rvce_encode_bitstream(struct pipe_video_codec *encoder,
RVID_ERR("Can't create feedback buffer.\n");
return;
}
+ if (!enc->cs->cdw)
+ enc->session(enc);
enc->encode(enc);
enc->feedback(enc);
}
struct rvce_cpb_slot *slot = LIST_ENTRY(
struct rvce_cpb_slot, enc->cpb_slots.prev, list);
- flush(enc);
+ if (!enc->dual_inst || enc->bs_idx > 1)
+ flush(enc);
/* update the CPB backtrack with the just encoded frame */
slot->picture_type = enc->pic.picture_type;
*/
static void rvce_flush(struct pipe_video_codec *encoder)
{
+ struct rvce_encoder *enc = (struct rvce_encoder*)encoder;
+
+ flush(enc);
}
static void rvce_cs_flush(void *ctx, unsigned flags,
enc->use_vm = true;
if ((rscreen->info.drm_major > 2) || (rscreen->info.drm_minor >= 42))
enc->use_vui = true;
- if (rscreen->info.family >= CHIP_TONGA)
- enc->use_2p = true;
+ if (rscreen->info.family >= CHIP_TONGA &&
+ rscreen->info.family != CHIP_STONEY)
+ enc->dual_pipe = true;
+ /* TODO enable B frame with dual instance */
+ if ((rscreen->info.family >= CHIP_TONGA) &&
+ (templ->max_references == 1) &&
+ (rscreen->info.vce_harvest_config == 0))
+ enc->dual_inst = true;
enc->base = *templ;
enc->base.context = context;
cpb_size = cpb_size * align(tmp_surf->npix_y, 16);
cpb_size = cpb_size * 3 / 2;
cpb_size = cpb_size * enc->cpb_num;
- if (enc->use_2p)
+ if (enc->dual_pipe)
cpb_size += RVCE_MAX_AUX_BUFFER_NUM *
- RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE;
+ RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE * 2;
tmp_buf->destroy(tmp_buf);
if (!rvid_create_buffer(enc->screen, &enc->cpb, cpb_size, PIPE_USAGE_DEFAULT)) {
RVID_ERR("Can't create CPB buffer.\n");
case FW_50_0_1:
case FW_50_1_2:
+ case FW_50_10_2:
+ case FW_50_17_3:
radeon_vce_50_init(enc);
break;
+ case FW_52_0_3:
+ radeon_vce_52_init(enc);
+ break;
+
default:
goto error;
}
*/
bool rvce_is_fw_version_supported(struct r600_common_screen *rscreen)
{
- return rscreen->info.vce_fw_version == FW_40_2_2 ||
- rscreen->info.vce_fw_version == FW_50_0_1 ||
- rscreen->info.vce_fw_version == FW_50_1_2;
+ switch (rscreen->info.vce_fw_version) {
+ case FW_40_2_2:
+ case FW_50_0_1:
+ case FW_50_1_2:
+ case FW_50_10_2:
+ case FW_50_17_3:
+ case FW_52_0_3:
+ return true;
+ default:
+ return false;
+ }
}
/**
*/
void rvce_add_buffer(struct rvce_encoder *enc, struct radeon_winsys_cs_handle *buf,
enum radeon_bo_usage usage, enum radeon_bo_domain domain,
- uint32_t offset)
+ signed offset)
{
int reloc_idx;
- reloc_idx = enc->ws->cs_add_reloc(enc->cs, buf, usage, domain, RADEON_PRIO_MIN);
+ reloc_idx = enc->ws->cs_add_buffer(enc->cs, buf, usage, domain, RADEON_PRIO_VCE);
if (enc->use_vm) {
uint64_t addr;
addr = enc->ws->buffer_get_virtual_address(buf);