gallium/radeon: do not reallocate user memory buffers

[mesa.git] / src / gallium / drivers / radeon / radeon_vce.h

diff --git a/src/gallium/drivers/radeon/radeon_vce.h b/src/gallium/drivers/radeon/radeon_vce.h
index 66c547855b1f49308d66c63f326f9b2a0a2e84b9..8290e94fda75890525d1f560dec27c3d8920ae0b 100644 (file)
--- a/src/gallium/drivers/radeon/radeon_vce.h
+++ b/src/gallium/drivers/radeon/radeon_vce.h
@@ -43,11 +43,14 @@
 #define RVCE_READWRITE(buf, domain, off) rvce_add_buffer(enc, (buf), RADEON_USAGE_READWRITE, (domain), (off))
 #define RVCE_END() *begin = (&enc->cs->buf[enc->cs->cdw] - begin) * 4; }
 
+#define RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE (4096 * 16 * 2.5)
+#define RVCE_MAX_AUX_BUFFER_NUM 4
+
 struct r600_common_screen;
 
 /* driver dependent callback */
 typedef void (*rvce_get_buffer)(struct pipe_resource *resource,
-                               struct radeon_winsys_cs_handle **handle,
+                               struct pb_buffer **handle,
                                struct radeon_surf **surface);
 
 /* Coded picture buffer slot */
@@ -74,8 +77,12 @@ struct rvce_encoder {
        void (*motion_estimation)(struct rvce_encoder *enc);
        void (*rdo)(struct rvce_encoder *enc);
        void (*vui)(struct rvce_encoder *enc);
+       void (*config)(struct rvce_encoder *enc);
        void (*encode)(struct rvce_encoder *enc);
        void (*destroy)(struct rvce_encoder *enc);
+       void (*task_info)(struct rvce_encoder *enc, uint32_t op,
+                         uint32_t dep, uint32_t fb_idx,
+                         uint32_t ring_idx);
 
        unsigned                        stream_handle;
 
@@ -85,11 +92,11 @@ struct rvce_encoder {
 
        rvce_get_buffer                 get_buffer;
 
-       struct radeon_winsys_cs_handle* handle;
+       struct pb_buffer*       handle;
        struct radeon_surf*             luma;
        struct radeon_surf*             chroma;
 
-       struct radeon_winsys_cs_handle* bs_handle;
+       struct pb_buffer*       bs_handle;
        unsigned                        bs_size;
 
        struct rvce_cpb_slot            *cpb_array;
@@ -99,8 +106,14 @@ struct rvce_encoder {
        struct rvid_buffer              *fb;
        struct rvid_buffer              cpb;
        struct pipe_h264_enc_picture_desc pic;
+
+       unsigned                        task_info_idx;
+       unsigned                        bs_idx;
+
        bool                            use_vm;
        bool                            use_vui;
+       bool                            dual_pipe;
+       bool                            dual_inst;
 };
 
 /* CPB handling functions */
@@ -108,7 +121,7 @@ struct rvce_cpb_slot *current_slot(struct rvce_encoder *enc);
 struct rvce_cpb_slot *l0_slot(struct rvce_encoder *enc);
 struct rvce_cpb_slot *l1_slot(struct rvce_encoder *enc);
 void rvce_frame_offset(struct rvce_encoder *enc, struct rvce_cpb_slot *slot,
-                      unsigned *luma_offset, unsigned *chroma_offset);
+                      signed *luma_offset, signed *chroma_offset);
 
 struct pipe_video_codec *rvce_create_encoder(struct pipe_context *context,
                                             const struct pipe_video_codec *templat,
@@ -117,9 +130,9 @@ struct pipe_video_codec *rvce_create_encoder(struct pipe_context *context,
 
 bool rvce_is_fw_version_supported(struct r600_common_screen *rscreen);
 
-void rvce_add_buffer(struct rvce_encoder *enc, struct radeon_winsys_cs_handle *buf,
+void rvce_add_buffer(struct rvce_encoder *enc, struct pb_buffer *buf,
                     enum radeon_bo_usage usage, enum radeon_bo_domain domain,
-                    uint32_t offset);
+                    signed offset);
 
 /* init vce fw 40.2.2 specific callbacks */
 void radeon_vce_40_2_2_init(struct rvce_encoder *enc);
@@ -127,4 +140,7 @@ void radeon_vce_40_2_2_init(struct rvce_encoder *enc);
 /* init vce fw 50 specific callbacks */
 void radeon_vce_50_init(struct rvce_encoder *enc);
 
+/* init vce fw 52 specific callbacks */
+void radeon_vce_52_init(struct rvce_encoder *enc);
+
 #endif