configure.ac: use pkg-config for libelf

[mesa.git] / src / gallium / drivers / radeon / radeon_vce_50.c

diff --git a/src/gallium/drivers/radeon/radeon_vce_50.c b/src/gallium/drivers/radeon/radeon_vce_50.c
index a11cc6a2860c4aa261fbebc5f806fdf901665074..82e7ad2be76ea16b9d81df9765fb900aaa515be1 100644 (file)
--- a/src/gallium/drivers/radeon/radeon_vce_50.c
+++ b/src/gallium/drivers/radeon/radeon_vce_50.c
@@ -44,18 +44,6 @@
 #include "radeon_video.h"
 #include "radeon_vce.h"
 
-static void task_info(struct rvce_encoder *enc, uint32_t taskOperation)
-{
-       RVCE_BEGIN(0x00000002); // task info
-       RVCE_CS(0xffffffff); // offsetOfNextTaskInfo
-       RVCE_CS(taskOperation); // taskOperation
-       RVCE_CS(0x00000000); // referencePictureDependency
-       RVCE_CS(0x00000000); // collocateFlagDependency
-       RVCE_CS(0x00000000); // feedbackIndex
-       RVCE_CS(0x00000000); // videoBitstreamRingIndex
-       RVCE_END();
-}
-
 static void rate_control(struct rvce_encoder *enc)
 {
        RVCE_BEGIN(0x04000005); // rate control
@@ -90,17 +78,30 @@ static void rate_control(struct rvce_encoder *enc)
 
 static void encode(struct rvce_encoder *enc)
 {
+       signed luma_offset, chroma_offset, bs_offset;
+       unsigned dep, bs_idx = enc->bs_idx++;
        int i;
-       unsigned luma_offset, chroma_offset;
 
-       task_info(enc, 0x00000003);
+       if (enc->dual_inst) {
+               if (bs_idx == 0)
+                       dep = 1;
+               else if (enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_IDR)
+                       dep = 0;
+               else
+                       dep = 2;
+       } else
+               dep = 0;
+
+       enc->task_info(enc, 0x00000003, dep, 0, bs_idx);
 
        RVCE_BEGIN(0x05000001); // context buffer
-       RVCE_READWRITE(enc->cpb.res->cs_buf, enc->cpb.res->domains, 0); // encodeContextAddressHi/Lo
+       RVCE_READWRITE(enc->cpb.res->buf, enc->cpb.res->domains, 0); // encodeContextAddressHi/Lo
        RVCE_END();
 
+       bs_offset = -(signed)(bs_idx * enc->bs_size);
+
        RVCE_BEGIN(0x05000004); // video bitstream buffer
-       RVCE_WRITE(enc->bs_handle, RADEON_DOMAIN_GTT, 0); // videoBitstreamRingAddressHi/Lo
+       RVCE_WRITE(enc->bs_handle, RADEON_DOMAIN_GTT, bs_offset); // videoBitstreamRingAddressHi/Lo
        RVCE_CS(enc->bs_size); // videoBitstreamRingSize
        RVCE_END();