#include "radeon_video.h"
#include "radeon_vce.h"
-static void task_info(struct rvce_encoder *enc, uint32_t taskOperation)
-{
- RVCE_BEGIN(0x00000002); // task info
- RVCE_CS(0xffffffff); // offsetOfNextTaskInfo
- RVCE_CS(taskOperation); // taskOperation
- RVCE_CS(0x00000000); // referencePictureDependency
- RVCE_CS(0x00000000); // collocateFlagDependency
- RVCE_CS(0x00000000); // feedbackIndex
- RVCE_CS(0x00000000); // videoBitstreamRingIndex
- RVCE_END();
-}
-
static void rate_control(struct rvce_encoder *enc)
{
RVCE_BEGIN(0x04000005); // rate control
static void encode(struct rvce_encoder *enc)
{
+ signed luma_offset, chroma_offset, bs_offset;
+ unsigned dep, bs_idx = enc->bs_idx++;
int i;
- unsigned luma_offset, chroma_offset;
- task_info(enc, 0x00000003);
+ if (enc->dual_inst) {
+ if (bs_idx == 0)
+ dep = 1;
+ else if (enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_IDR)
+ dep = 0;
+ else
+ dep = 2;
+ } else
+ dep = 0;
+
+ enc->task_info(enc, 0x00000003, dep, 0, bs_idx);
RVCE_BEGIN(0x05000001); // context buffer
- RVCE_READWRITE(enc->cpb.res->cs_buf, enc->cpb.res->domains, 0); // encodeContextAddressHi
- RVCE_CS(0x00000000); // encodeContextAddressLo
+ RVCE_READWRITE(enc->cpb.res->buf, enc->cpb.res->domains, 0); // encodeContextAddressHi/Lo
RVCE_END();
+ bs_offset = -(signed)(bs_idx * enc->bs_size);
+
RVCE_BEGIN(0x05000004); // video bitstream buffer
- RVCE_WRITE(enc->bs_handle, RADEON_DOMAIN_GTT, 0); // videoBitstreamRingAddressHi
- RVCE_CS(0x00000000); // videoBitstreamRingAddressLo
+ RVCE_WRITE(enc->bs_handle, RADEON_DOMAIN_GTT, bs_offset); // videoBitstreamRingAddressHi/Lo
RVCE_CS(enc->bs_size); // videoBitstreamRingSize
RVCE_END();
RVCE_CS(0x00000000); // insertAUD
RVCE_CS(0x00000000); // endOfSequence
RVCE_CS(0x00000000); // endOfStream
- RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM, 0); // inputPictureLumaAddressHi
- RVCE_CS(enc->luma->level[0].offset); // inputPictureLumaAddressLo
- RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM, 0); // inputPictureChromaAddressHi
- RVCE_CS(enc->chroma->level[0].offset); // inputPictureChromaAddressLo
- RVCE_CS(align(enc->luma->npix_y, 16)); // encInputFrameYPitch
- RVCE_CS(enc->luma->level[0].pitch_bytes); // encInputPicLumaPitch
- RVCE_CS(enc->chroma->level[0].pitch_bytes); // encInputPicChromaPitch
+ RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM,
+ enc->luma->level[0].offset); // inputPictureLumaAddressHi/Lo
+ RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM,
+ enc->chroma->level[0].offset); // inputPictureChromaAddressHi/Lo
+ RVCE_CS(align(enc->luma->level[0].nblk_y, 16)); // encInputFrameYPitch
+ RVCE_CS(enc->luma->level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch
+ RVCE_CS(enc->chroma->level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch
if (enc->dual_pipe)
RVCE_CS(0x00000000); // encInputPic(Addr|Array)Mode,encDisable(TwoPipeMode|MBOffloading)
else
RVCE_END();
}
+void radeon_vce_50_get_param(struct rvce_encoder *enc, struct pipe_h264_enc_picture_desc *pic)
+{
+}
+
void radeon_vce_50_init(struct rvce_encoder *enc)
{
radeon_vce_40_2_2_init(enc);