radeon/vce: Move global function pointer si_get_pic_param to local encoder structure

[mesa.git] / src / gallium / drivers / radeon / radeon_vcn_dec.c

diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c b/src/gallium/drivers/radeon/radeon_vcn_dec.c
index 77bfe187674fae03213988b010dd18f5b59d9030..0f903b1629f5445fb0f142bf1d21e560bc089c97 100644 (file)
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
@@ -329,7 +329,8 @@ static rvcn_dec_message_hevc_t get_h265_msg(struct radeon_decoder *dec,
        }
 
        if (pic->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10) {
-               if (target->buffer_format == PIPE_FORMAT_P016) {
+               if (target->buffer_format == PIPE_FORMAT_P010 ||
+                       target->buffer_format == PIPE_FORMAT_P016) {
                        result.p010_mode = 1;
                        result.msb_mode = 1;
                } else {
@@ -530,7 +531,8 @@ static rvcn_dec_message_vp9_t get_vp9_msg(struct radeon_decoder *dec,
        result.ref_frame_sign_bias[2] = pic->picture_parameter.pic_fields.alt_ref_frame_sign_bias;
 
        if (pic->base.profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2) {
-               if (target->buffer_format == PIPE_FORMAT_P016) {
+               if (target->buffer_format == PIPE_FORMAT_P010 ||
+                       target->buffer_format == PIPE_FORMAT_P016) {
                        result.p010_mode = 1;
                        result.msb_mode = 1;
                } else {
@@ -840,7 +842,7 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
        decode->sc_coeff_size = 0;
 
        decode->sw_ctxt_size = RDECODE_SESSION_CONTEXT_SIZE;
-       decode->db_pitch = (((struct si_screen*)dec->screen)->info.family >= CHIP_ARCTURUS &&
+       decode->db_pitch = (((struct si_screen*)dec->screen)->info.family >= CHIP_RENOIR &&
                        dec->base.width > 32 && dec->stream_type == RDECODE_CODEC_VP9) ?
                        align(dec->base.width, 64) :
                        align(dec->base.width, 32) ;
@@ -938,13 +940,13 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
                        /* default probability + probability data */
                        ctx_size = 2304 * 5;
 
-                       if (((struct si_screen*)dec->screen)->info.family >= CHIP_ARCTURUS) {
+                       if (((struct si_screen*)dec->screen)->info.family >= CHIP_RENOIR) {
                                /* SRE collocated context data */
                                ctx_size += 32 * 2 * 128 * 68;
                                /* SMP collocated context data */
                                ctx_size += 9 * 64 * 2 * 128 * 68;
                                /* SDB left tile pixel */
-                               ctx_size += 8 * 2 * 8192;
+                               ctx_size += 8 * 2 * 2 * 8192;
                        } else {
                                ctx_size += 32 * 2 * 64 * 64;
                                ctx_size += 9 * 64 * 2 * 64 * 64;
@@ -1263,7 +1265,7 @@ static unsigned calc_dpb_size(struct radeon_decoder *dec)
        case PIPE_VIDEO_FORMAT_VP9:
                max_references = MAX2(max_references, 9);
 
-               dpb_size = (((struct si_screen*)dec->screen)->info.family >= CHIP_ARCTURUS) ?
+               dpb_size = (((struct si_screen*)dec->screen)->info.family >= CHIP_RENOIR) ?
                        (8192 * 4320 * 3 / 2) * max_references :
                        (4096 * 3000 * 3 / 2) * max_references;
 
@@ -1607,7 +1609,8 @@ struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
                dec->reg.data1 = RDECODE_VCN2_5_GPCOM_VCPU_DATA1;
                dec->reg.cmd = RDECODE_VCN2_5_GPCOM_VCPU_CMD;
                dec->reg.cntl = RDECODE_VCN2_5_ENGINE_CNTL;
-       } else if (sctx->family >= CHIP_NAVI10) {
+               dec->jpg.direct_reg = true;
+       } else if (sctx->family >= CHIP_NAVI10 || sctx->family == CHIP_RENOIR) {
                dec->reg.data0 = RDECODE_VCN2_GPCOM_VCPU_DATA0;
                dec->reg.data1 = RDECODE_VCN2_GPCOM_VCPU_DATA1;
                dec->reg.cmd = RDECODE_VCN2_GPCOM_VCPU_CMD;