iris: Implement pipe_screen::resource_get_param

[mesa.git] / src / gallium / drivers / radeon / radeon_vcn_dec.c

diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c b/src/gallium/drivers/radeon/radeon_vcn_dec.c
index 99293411b0dc89b694ca148c9875a274c4df7e02..77bfe187674fae03213988b010dd18f5b59d9030 100644 (file)
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
@@ -56,6 +56,11 @@
 #define RDECODE_VCN2_GPCOM_VCPU_DATA1          (0x505 << 2)
 #define RDECODE_VCN2_ENGINE_CNTL               (0x506 << 2)
 
+#define RDECODE_VCN2_5_GPCOM_VCPU_CMD          0x3c
+#define RDECODE_VCN2_5_GPCOM_VCPU_DATA0        0x40
+#define RDECODE_VCN2_5_GPCOM_VCPU_DATA1        0x44
+#define RDECODE_VCN2_5_ENGINE_CNTL             0x9b4
+
 #define NUM_MPEG2_REFS                 6
 #define NUM_H264_REFS                  17
 #define NUM_VC1_REFS                   5
@@ -835,7 +840,7 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
        decode->sc_coeff_size = 0;
 
        decode->sw_ctxt_size = RDECODE_SESSION_CONTEXT_SIZE;
-       decode->db_pitch = (((struct si_screen*)dec->screen)->info.family >= CHIP_NAVI10 &&
+       decode->db_pitch = (((struct si_screen*)dec->screen)->info.family >= CHIP_ARCTURUS &&
                        dec->base.width > 32 && dec->stream_type == RDECODE_CODEC_VP9) ?
                        align(dec->base.width, 64) :
                        align(dec->base.width, 32) ;
@@ -933,7 +938,7 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
                        /* default probability + probability data */
                        ctx_size = 2304 * 5;
 
-                       if (((struct si_screen*)dec->screen)->info.family >= CHIP_NAVI10) {
+                       if (((struct si_screen*)dec->screen)->info.family >= CHIP_ARCTURUS) {
                                /* SRE collocated context data */
                                ctx_size += 32 * 2 * 128 * 68;
                                /* SMP collocated context data */
@@ -1258,7 +1263,7 @@ static unsigned calc_dpb_size(struct radeon_decoder *dec)
        case PIPE_VIDEO_FORMAT_VP9:
                max_references = MAX2(max_references, 9);
 
-               dpb_size = (((struct si_screen*)dec->screen)->info.family >= CHIP_NAVI10) ?
+               dpb_size = (((struct si_screen*)dec->screen)->info.family >= CHIP_ARCTURUS) ?
                        (8192 * 4320 * 3 / 2) * max_references :
                        (4096 * 3000 * 3 / 2) * max_references;
 
@@ -1597,16 +1602,23 @@ struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
        }
        si_vid_clear_buffer(context, &dec->sessionctx);
 
-       if (sctx->family >= CHIP_NAVI10) {
+       if (sctx->family == CHIP_ARCTURUS) {
+               dec->reg.data0 = RDECODE_VCN2_5_GPCOM_VCPU_DATA0;
+               dec->reg.data1 = RDECODE_VCN2_5_GPCOM_VCPU_DATA1;
+               dec->reg.cmd = RDECODE_VCN2_5_GPCOM_VCPU_CMD;
+               dec->reg.cntl = RDECODE_VCN2_5_ENGINE_CNTL;
+       } else if (sctx->family >= CHIP_NAVI10) {
                dec->reg.data0 = RDECODE_VCN2_GPCOM_VCPU_DATA0;
                dec->reg.data1 = RDECODE_VCN2_GPCOM_VCPU_DATA1;
                dec->reg.cmd = RDECODE_VCN2_GPCOM_VCPU_CMD;
                dec->reg.cntl = RDECODE_VCN2_ENGINE_CNTL;
+               dec->jpg.direct_reg = true;
        } else {
                dec->reg.data0 = RDECODE_VCN1_GPCOM_VCPU_DATA0;
                dec->reg.data1 = RDECODE_VCN1_GPCOM_VCPU_DATA1;
                dec->reg.cmd = RDECODE_VCN1_GPCOM_VCPU_CMD;
                dec->reg.cntl = RDECODE_VCN1_ENGINE_CNTL;
+               dec->jpg.direct_reg = false;
        }
 
        map_msg_fb_it_probs_buf(dec);