winsys/radeon: use the common job queue for multithreaded command submission v2
[mesa.git] / src / gallium / drivers / radeon / radeon_video.c
index 24b0eed51d219da091d8d8668f6c9ae3dec3f2ae..aba1404d1cb16caaeaebf322e9459fdb665d8915 100644 (file)
@@ -122,7 +122,7 @@ void rvid_clear_buffer(struct pipe_context *context, struct rvid_buffer* buffer)
        struct r600_common_context *rctx = (struct r600_common_context*)context;
 
        rctx->clear_buffer(context, &buffer->res->b.b, 0, buffer->res->buf->size,
-                          0, false);
+                          0, R600_COHERENCY_NONE);
        context->flush(context, NULL, 0);
 }
 
@@ -130,7 +130,7 @@ void rvid_clear_buffer(struct pipe_context *context, struct rvid_buffer* buffer)
  * join surfaces into the same buffer with identical tiling params
  * sumup their sizes and replace the backend buffers with a single bo
  */
-void rvid_join_surfaces(struct radeon_winsys* ws, unsigned bind,
+void rvid_join_surfaces(struct radeon_winsys* ws,
                        struct pb_buffer** buffers[VL_NUM_COMPONENTS],
                        struct radeon_surf *surfaces[VL_NUM_COMPONENTS])
 {
@@ -165,7 +165,7 @@ void rvid_join_surfaces(struct radeon_winsys* ws, unsigned bind,
 
                /* adjust the texture layer offsets */
                off = align(off, surfaces[i]->bo_alignment);
-               for (j = 0; j < Elements(surfaces[i]->level); ++j)
+               for (j = 0; j < ARRAY_SIZE(surfaces[i]->level); ++j)
                        surfaces[i]->level[j].offset += off;
                off += surfaces[i]->bo_size;
        }
@@ -185,7 +185,7 @@ void rvid_join_surfaces(struct radeon_winsys* ws, unsigned bind,
        /* TODO: 2D tiling workaround */
        alignment *= 2;
 
-       pb = ws->buffer_create(ws, size, alignment, bind, RADEON_DOMAIN_VRAM, 0);
+       pb = ws->buffer_create(ws, size, alignment, RADEON_DOMAIN_VRAM, 0);
        if (!pb)
                return;
 
@@ -298,7 +298,7 @@ int rvid_get_video_param(struct pipe_screen *screen,
                case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
                case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
                case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
-                       return 41;
+                       return (rscreen->family < CHIP_TONGA) ? 41 : 52;
                case PIPE_VIDEO_PROFILE_HEVC_MAIN:
                case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
                        return 186;