winsys/radeon: use the common job queue for multithreaded command submission v2
[mesa.git] / src / gallium / drivers / radeon / radeon_video.c
index 5a8d18762d90d8dc63bde20bc7ee3f1862dc0b70..aba1404d1cb16caaeaebf322e9459fdb665d8915 100644 (file)
@@ -89,11 +89,11 @@ bool rvid_resize_buffer(struct pipe_screen *screen, struct radeon_winsys_cs *cs,
        if (!rvid_create_buffer(screen, new_buf, new_size, new_buf->usage))
                goto error;
 
-       src = ws->buffer_map(old_buf.res->cs_buf, cs, PIPE_TRANSFER_READ);
+       src = ws->buffer_map(old_buf.res->buf, cs, PIPE_TRANSFER_READ);
        if (!src)
                goto error;
 
-       dst = ws->buffer_map(new_buf->res->cs_buf, cs, PIPE_TRANSFER_WRITE);
+       dst = ws->buffer_map(new_buf->res->buf, cs, PIPE_TRANSFER_WRITE);
        if (!dst)
                goto error;
 
@@ -103,14 +103,14 @@ bool rvid_resize_buffer(struct pipe_screen *screen, struct radeon_winsys_cs *cs,
                dst += bytes;
                memset(dst, 0, new_size);
        }
-       ws->buffer_unmap(new_buf->res->cs_buf);
-       ws->buffer_unmap(old_buf.res->cs_buf);
+       ws->buffer_unmap(new_buf->res->buf);
+       ws->buffer_unmap(old_buf.res->buf);
        rvid_destroy_buffer(&old_buf);
        return true;
 
 error:
        if (src)
-               ws->buffer_unmap(old_buf.res->cs_buf);
+               ws->buffer_unmap(old_buf.res->buf);
        rvid_destroy_buffer(new_buf);
        *new_buf = old_buf;
        return false;
@@ -122,7 +122,7 @@ void rvid_clear_buffer(struct pipe_context *context, struct rvid_buffer* buffer)
        struct r600_common_context *rctx = (struct r600_common_context*)context;
 
        rctx->clear_buffer(context, &buffer->res->b.b, 0, buffer->res->buf->size,
-                          0, false);
+                          0, R600_COHERENCY_NONE);
        context->flush(context, NULL, 0);
 }
 
@@ -130,7 +130,7 @@ void rvid_clear_buffer(struct pipe_context *context, struct rvid_buffer* buffer)
  * join surfaces into the same buffer with identical tiling params
  * sumup their sizes and replace the backend buffers with a single bo
  */
-void rvid_join_surfaces(struct radeon_winsys* ws, unsigned bind,
+void rvid_join_surfaces(struct radeon_winsys* ws,
                        struct pb_buffer** buffers[VL_NUM_COMPONENTS],
                        struct radeon_surf *surfaces[VL_NUM_COMPONENTS])
 {
@@ -165,7 +165,7 @@ void rvid_join_surfaces(struct radeon_winsys* ws, unsigned bind,
 
                /* adjust the texture layer offsets */
                off = align(off, surfaces[i]->bo_alignment);
-               for (j = 0; j < Elements(surfaces[i]->level); ++j)
+               for (j = 0; j < ARRAY_SIZE(surfaces[i]->level); ++j)
                        surfaces[i]->level[j].offset += off;
                off += surfaces[i]->bo_size;
        }
@@ -185,7 +185,7 @@ void rvid_join_surfaces(struct radeon_winsys* ws, unsigned bind,
        /* TODO: 2D tiling workaround */
        alignment *= 2;
 
-       pb = ws->buffer_create(ws, size, alignment, bind, RADEON_DOMAIN_VRAM, 0);
+       pb = ws->buffer_create(ws, size, alignment, RADEON_DOMAIN_VRAM, 0);
        if (!pb)
                return;
 
@@ -205,11 +205,12 @@ int rvid_get_video_param(struct pipe_screen *screen,
                         enum pipe_video_cap param)
 {
        struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
+       enum pipe_video_format codec = u_reduce_video_profile(profile);
 
        if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
                switch (param) {
                case PIPE_VIDEO_CAP_SUPPORTED:
-                       return u_reduce_video_profile(profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
+                       return codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
                                rvce_is_fw_version_supported(rscreen);
                case PIPE_VIDEO_CAP_NPOT_TEXTURES:
                        return 1;
@@ -232,38 +233,26 @@ int rvid_get_video_param(struct pipe_screen *screen,
                }
        }
 
-       /* UVD 2.x limits */
-       if (rscreen->family < CHIP_PALM) {
-               enum pipe_video_format codec = u_reduce_video_profile(profile);
-               switch (param) {
-               case PIPE_VIDEO_CAP_SUPPORTED:
-                       /* no support for MPEG4 */
-                       return codec != PIPE_VIDEO_FORMAT_MPEG4 &&
-                              /* FIXME: VC-1 simple/main profile is broken */
-                              profile != PIPE_VIDEO_PROFILE_VC1_SIMPLE &&
-                              profile != PIPE_VIDEO_PROFILE_VC1_MAIN;
-               case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
-               case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
-                       /* MPEG2 only with shaders and no support for
-                          interlacing on R6xx style UVD */
-                       return codec != PIPE_VIDEO_FORMAT_MPEG12 &&
-                              rscreen->family > CHIP_RV770;
-               default:
-                       break;
-               }
-       }
-
        switch (param) {
        case PIPE_VIDEO_CAP_SUPPORTED:
-               switch (u_reduce_video_profile(profile)) {
+               switch (codec) {
                case PIPE_VIDEO_FORMAT_MPEG12:
+                       return profile != PIPE_VIDEO_PROFILE_MPEG1;
                case PIPE_VIDEO_FORMAT_MPEG4:
                case PIPE_VIDEO_FORMAT_MPEG4_AVC:
-                       return entrypoint != PIPE_VIDEO_ENTRYPOINT_ENCODE;
+                       if (rscreen->family < CHIP_PALM)
+                               /* no support for MPEG4 */
+                               return codec != PIPE_VIDEO_FORMAT_MPEG4;
+                       return true;
                case PIPE_VIDEO_FORMAT_VC1:
-                       /* FIXME: VC-1 simple/main profile is broken */
-                       return profile == PIPE_VIDEO_PROFILE_VC1_ADVANCED &&
-                              entrypoint != PIPE_VIDEO_ENTRYPOINT_ENCODE;
+                       return true;
+               case PIPE_VIDEO_FORMAT_HEVC:
+                       /* Carrizo only supports HEVC Main */
+                       if (rscreen->family >= CHIP_STONEY)
+                               return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
+                                       profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
+                       else if (rscreen->family >= CHIP_CARRIZO)
+                               return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
                default:
                        return false;
                }
@@ -272,13 +261,21 @@ int rvid_get_video_param(struct pipe_screen *screen,
        case PIPE_VIDEO_CAP_MAX_WIDTH:
                return (rscreen->family < CHIP_TONGA) ? 2048 : 4096;
        case PIPE_VIDEO_CAP_MAX_HEIGHT:
-               return (rscreen->family < CHIP_TONGA) ? 1152 : 2304;
+               return (rscreen->family < CHIP_TONGA) ? 1152 : 4096;
        case PIPE_VIDEO_CAP_PREFERED_FORMAT:
                return PIPE_FORMAT_NV12;
        case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
-               return true;
        case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
-               return true;
+               if (rscreen->family < CHIP_PALM) {
+                       /* MPEG2 only with shaders and no support for
+                          interlacing on R6xx style UVD */
+                       return codec != PIPE_VIDEO_FORMAT_MPEG12 &&
+                              rscreen->family > CHIP_RV770;
+               } else {
+                       if (u_reduce_video_profile(profile) == PIPE_VIDEO_FORMAT_HEVC)
+                               return false; //The firmware doesn't support interlaced HEVC.
+                       return true;
+               }
        case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
                return true;
        case PIPE_VIDEO_CAP_MAX_LEVEL:
@@ -301,7 +298,10 @@ int rvid_get_video_param(struct pipe_screen *screen,
                case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
                case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
                case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
-                       return 41;
+                       return (rscreen->family < CHIP_TONGA) ? 41 : 52;
+               case PIPE_VIDEO_PROFILE_HEVC_MAIN:
+               case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
+                       return 186;
                default:
                        return 0;
                }