radeonsi: rename query definitions R600_ -> SI_

[mesa.git] / src / gallium / drivers / radeon / radeon_winsys.h

diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h
index d1c761f4eeab8a136813435c64348cc09b5dd9ea..157b2e405504957391c3d8ec40d721e95b485274 100644 (file)
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -1,6 +1,8 @@
 /*
  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -53,6 +55,7 @@ enum radeon_bo_flag { /* bitfield */
     RADEON_FLAG_SPARSE =        (1 << 3),
     RADEON_FLAG_NO_INTERPROCESS_SHARING = (1 << 4),
     RADEON_FLAG_READ_ONLY =     (1 << 5),
+    RADEON_FLAG_32BIT =    (1 << 6),
 };
 
 enum radeon_bo_usage { /* bitfield */
@@ -582,6 +585,12 @@ struct radeon_winsys {
     void (*cs_add_fence_dependency)(struct radeon_winsys_cs *cs,
                                     struct pipe_fence_handle *fence);
 
+    /**
+     * Signal a syncobj when the CS finishes execution.
+     */
+    void (*cs_add_syncobj_signal)(struct radeon_winsys_cs *cs,
+                                 struct pipe_fence_handle *fence);
+
     /**
      * Wait for the fence and return true if the fence has been signalled.
      * The timeout of 0 will only return the status.
@@ -598,6 +607,12 @@ struct radeon_winsys {
     void (*fence_reference)(struct pipe_fence_handle **dst,
                             struct pipe_fence_handle *src);
 
+    /**
+     * Create a new fence object corresponding to the given syncobj fd.
+     */
+    struct pipe_fence_handle *(*fence_import_syncobj)(struct radeon_winsys *ws,
+                                                     int fd);
+
     /**
      * Create a new fence object corresponding to the given sync_file.
      */
@@ -610,6 +625,11 @@ struct radeon_winsys {
     int (*fence_export_sync_file)(struct radeon_winsys *ws,
                                  struct pipe_fence_handle *fence);
 
+    /**
+     * Return a sync file FD that is already signalled.
+     */
+    int (*export_signalled_sync_file)(struct radeon_winsys *ws);
+
     /**
      * Initialize surface
      *
@@ -655,9 +675,13 @@ static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
 enum radeon_heap {
     RADEON_HEAP_VRAM_NO_CPU_ACCESS,
     RADEON_HEAP_VRAM_READ_ONLY,
+    RADEON_HEAP_VRAM_READ_ONLY_32BIT,
+    RADEON_HEAP_VRAM_32BIT,
     RADEON_HEAP_VRAM,
     RADEON_HEAP_GTT_WC,
     RADEON_HEAP_GTT_WC_READ_ONLY,
+    RADEON_HEAP_GTT_WC_READ_ONLY_32BIT,
+    RADEON_HEAP_GTT_WC_32BIT,
     RADEON_HEAP_GTT,
     RADEON_MAX_SLAB_HEAPS,
     RADEON_MAX_CACHED_HEAPS = RADEON_MAX_SLAB_HEAPS,
@@ -668,10 +692,14 @@ static inline enum radeon_bo_domain radeon_domain_from_heap(enum radeon_heap hea
     switch (heap) {
     case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
     case RADEON_HEAP_VRAM_READ_ONLY:
+    case RADEON_HEAP_VRAM_READ_ONLY_32BIT:
+    case RADEON_HEAP_VRAM_32BIT:
     case RADEON_HEAP_VRAM:
         return RADEON_DOMAIN_VRAM;
     case RADEON_HEAP_GTT_WC:
     case RADEON_HEAP_GTT_WC_READ_ONLY:
+    case RADEON_HEAP_GTT_WC_READ_ONLY_32BIT:
+    case RADEON_HEAP_GTT_WC_32BIT:
     case RADEON_HEAP_GTT:
         return RADEON_DOMAIN_GTT;
     default:
@@ -682,50 +710,35 @@ static inline enum radeon_bo_domain radeon_domain_from_heap(enum radeon_heap hea
 
 static inline unsigned radeon_flags_from_heap(enum radeon_heap heap)
 {
+    unsigned flags = RADEON_FLAG_NO_INTERPROCESS_SHARING |
+                     (heap != RADEON_HEAP_GTT ? RADEON_FLAG_GTT_WC : 0);
+
     switch (heap) {
     case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
-        return RADEON_FLAG_GTT_WC |
-               RADEON_FLAG_NO_CPU_ACCESS |
-               RADEON_FLAG_NO_INTERPROCESS_SHARING;
+        return flags |
+               RADEON_FLAG_NO_CPU_ACCESS;
 
     case RADEON_HEAP_VRAM_READ_ONLY:
-        return RADEON_FLAG_GTT_WC |
-               RADEON_FLAG_NO_INTERPROCESS_SHARING |
-               RADEON_FLAG_READ_ONLY;
-
-    case RADEON_HEAP_VRAM:
-    case RADEON_HEAP_GTT_WC:
-        return RADEON_FLAG_GTT_WC |
-               RADEON_FLAG_NO_INTERPROCESS_SHARING;
-
     case RADEON_HEAP_GTT_WC_READ_ONLY:
-        return RADEON_FLAG_GTT_WC |
-               RADEON_FLAG_NO_INTERPROCESS_SHARING |
+        return flags |
                RADEON_FLAG_READ_ONLY;
 
-    case RADEON_HEAP_GTT:
-    default:
-        return RADEON_FLAG_NO_INTERPROCESS_SHARING;
-    }
-}
+    case RADEON_HEAP_VRAM_READ_ONLY_32BIT:
+    case RADEON_HEAP_GTT_WC_READ_ONLY_32BIT:
+        return flags |
+               RADEON_FLAG_READ_ONLY |
+               RADEON_FLAG_32BIT;
+
+    case RADEON_HEAP_VRAM_32BIT:
+    case RADEON_HEAP_GTT_WC_32BIT:
+        return flags |
+               RADEON_FLAG_32BIT;
 
-/* The pb cache bucket is chosen to minimize pb_cache misses.
- * It must be between 0 and 3 inclusive.
- */
-static inline unsigned radeon_get_pb_cache_bucket_index(enum radeon_heap heap)
-{
-    switch (heap) {
-    case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
-        return 0;
-    case RADEON_HEAP_VRAM_READ_ONLY:
     case RADEON_HEAP_VRAM:
-        return 1;
     case RADEON_HEAP_GTT_WC:
-    case RADEON_HEAP_GTT_WC_READ_ONLY:
-        return 2;
     case RADEON_HEAP_GTT:
     default:
-        return 3;
+        return flags;
     }
 }
 
@@ -746,32 +759,53 @@ static inline int radeon_get_heap_index(enum radeon_bo_domain domain,
     if (flags & ~(RADEON_FLAG_GTT_WC |
                   RADEON_FLAG_NO_CPU_ACCESS |
                   RADEON_FLAG_NO_INTERPROCESS_SHARING |
-                  RADEON_FLAG_READ_ONLY))
+                  RADEON_FLAG_READ_ONLY |
+                  RADEON_FLAG_32BIT))
         return -1;
 
     switch (domain) {
     case RADEON_DOMAIN_VRAM:
-        switch (flags & (RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_READ_ONLY)) {
+        switch (flags & (RADEON_FLAG_NO_CPU_ACCESS |
+                         RADEON_FLAG_READ_ONLY |
+                         RADEON_FLAG_32BIT)) {
+        case RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT:
         case RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_READ_ONLY:
             assert(!"NO_CPU_ACCESS | READ_ONLY doesn't make sense");
             return -1;
+        case RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_32BIT:
+            assert(!"NO_CPU_ACCESS with 32BIT is disallowed");
+            return -1;
         case RADEON_FLAG_NO_CPU_ACCESS:
             return RADEON_HEAP_VRAM_NO_CPU_ACCESS;
+        case RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT:
+            return RADEON_HEAP_VRAM_READ_ONLY_32BIT;
         case RADEON_FLAG_READ_ONLY:
             return RADEON_HEAP_VRAM_READ_ONLY;
+        case RADEON_FLAG_32BIT:
+            return RADEON_HEAP_VRAM_32BIT;
         case 0:
             return RADEON_HEAP_VRAM;
         }
         break;
     case RADEON_DOMAIN_GTT:
-        switch (flags & (RADEON_FLAG_GTT_WC | RADEON_FLAG_READ_ONLY)) {
+        switch (flags & (RADEON_FLAG_GTT_WC |
+                         RADEON_FLAG_READ_ONLY |
+                         RADEON_FLAG_32BIT)) {
+        case RADEON_FLAG_GTT_WC | RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT:
+            return RADEON_HEAP_GTT_WC_READ_ONLY_32BIT;
         case RADEON_FLAG_GTT_WC | RADEON_FLAG_READ_ONLY:
             return RADEON_HEAP_GTT_WC_READ_ONLY;
+        case RADEON_FLAG_GTT_WC | RADEON_FLAG_32BIT:
+            return RADEON_HEAP_GTT_WC_32BIT;
         case RADEON_FLAG_GTT_WC:
             return RADEON_HEAP_GTT_WC;
+        case RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT:
         case RADEON_FLAG_READ_ONLY:
             assert(!"READ_ONLY without WC is disallowed");
             return -1;
+        case RADEON_FLAG_32BIT:
+            assert(!"32BIT without WC is disallowed");
+            return -1;
         case 0:
             return RADEON_HEAP_GTT;
         }