#include "pipebuffer/pb_buffer.h"
-#include "amd/common/amd_family.h"
+#include "amd/common/ac_gpu_info.h"
+#include "amd/common/ac_surface.h"
#define RADEON_FLUSH_ASYNC (1 << 0)
#define RADEON_FLUSH_END_OF_FRAME (1 << 1)
RADEON_FLAG_GTT_WC = (1 << 0),
RADEON_FLAG_CPU_ACCESS = (1 << 1),
RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
- RADEON_FLAG_HANDLE = (1 << 3), /* the buffer most not be suballocated */
+ RADEON_FLAG_HANDLE = (1 << 3), /* the buffer must not be suballocated */
+ RADEON_FLAG_SPARSE = (1 << 4),
};
enum radeon_bo_usage { /* bitfield */
RADEON_USAGE_SYNCHRONIZED = 8
};
+#define RADEON_SPARSE_PAGE_SIZE (64 * 1024)
+
enum ring_type {
RING_GFX = 0,
RING_COMPUTE,
RADEON_MAPPED_VRAM,
RADEON_MAPPED_GTT,
RADEON_BUFFER_WAIT_TIME_NS,
+ RADEON_NUM_MAPPED_BUFFERS,
RADEON_TIMESTAMP,
RADEON_NUM_GFX_IBS,
+ RADEON_NUM_SDMA_IBS,
RADEON_NUM_BYTES_MOVED,
RADEON_NUM_EVICTIONS,
+ RADEON_NUM_VRAM_CPU_PAGE_FAULTS,
RADEON_VRAM_USAGE,
+ RADEON_VRAM_VIS_USAGE,
RADEON_GTT_USAGE,
RADEON_GPU_TEMPERATURE, /* DRM 2.42.0 */
RADEON_CURRENT_SCLK,
RADEON_CURRENT_MCLK,
RADEON_GPU_RESET_COUNTER, /* DRM 2.43.0 */
+ RADEON_CS_THREAD_TIME,
};
/* Each group of four has the same priority. */
uint64_t used_gart;
};
-struct radeon_info {
- /* PCI info: domain:bus:dev:func */
- uint32_t pci_domain;
- uint32_t pci_bus;
- uint32_t pci_dev;
- uint32_t pci_func;
-
- /* Device info. */
- uint32_t pci_id;
- enum radeon_family family;
- enum chip_class chip_class;
- uint32_t gart_page_size;
- uint64_t gart_size;
- uint64_t vram_size;
- uint64_t max_alloc_size;
- uint32_t min_alloc_size;
- bool has_dedicated_vram;
- bool has_virtual_memory;
- bool gfx_ib_pad_with_type2;
- bool has_sdma;
- bool has_uvd;
- uint32_t uvd_fw_version;
- uint32_t vce_fw_version;
- uint32_t me_fw_version;
- uint32_t pfp_fw_version;
- uint32_t ce_fw_version;
- uint32_t vce_harvest_config;
- uint32_t clock_crystal_freq;
-
- /* Kernel info. */
- uint32_t drm_major; /* version */
- uint32_t drm_minor;
- uint32_t drm_patchlevel;
- bool has_userptr;
-
- /* Shader cores. */
- uint32_t r600_max_quad_pipes; /* wave size / 16 */
- uint32_t max_shader_clock;
- uint32_t num_good_compute_units;
- uint32_t max_se; /* shader engines */
- uint32_t max_sh_per_se; /* shader arrays per shader engine */
-
- /* Render backends (color + depth blocks). */
- uint32_t r300_num_gb_pipes;
- uint32_t r300_num_z_pipes;
- uint32_t r600_gb_backend_map; /* R600 harvest config */
- bool r600_gb_backend_map_valid;
- uint32_t r600_num_banks;
- uint32_t num_render_backends;
- uint32_t num_tile_pipes; /* pipe count from PIPE_CONFIG */
- uint32_t pipe_interleave_bytes;
- uint32_t enabled_rb_mask; /* GCN harvest config */
-
- /* Tile modes. */
- uint32_t si_tile_mode_array[32];
- uint32_t cik_macrotile_mode_array[16];
-};
-
/* Tiling info for display code, DRI sharing, and other data. */
struct radeon_bo_metadata {
/* Tiling flags describing the texture layout for display code
* and DRI sharing.
*/
- enum radeon_bo_layout microtile;
- enum radeon_bo_layout macrotile;
- unsigned pipe_config;
- unsigned bankw;
- unsigned bankh;
- unsigned tile_split;
- unsigned mtilea;
- unsigned num_banks;
- unsigned stride;
- bool scanout;
+ union {
+ struct {
+ enum radeon_bo_layout microtile;
+ enum radeon_bo_layout macrotile;
+ unsigned pipe_config;
+ unsigned bankw;
+ unsigned bankh;
+ unsigned tile_split;
+ unsigned mtilea;
+ unsigned num_banks;
+ unsigned stride;
+ bool scanout;
+ } legacy;
+
+ struct {
+ /* surface flags */
+ unsigned swizzle_mode:5;
+ } gfx9;
+ } u;
/* Additional metadata associated with the buffer, in bytes.
* The maximum size is 64 * 4. This is opaque for the winsys & kernel.
RADEON_FID_R300_CMASK_ACCESS,
};
-#define RADEON_SURF_MAX_LEVELS 15
-
-enum radeon_surf_mode {
- RADEON_SURF_MODE_LINEAR_ALIGNED = 1,
- RADEON_SURF_MODE_1D = 2,
- RADEON_SURF_MODE_2D = 3,
-};
-
-/* These are defined exactly like GB_TILE_MODEn.MICRO_TILE_MODE_NEW. */
-enum radeon_micro_mode {
- RADEON_MICRO_MODE_DISPLAY = 0,
- RADEON_MICRO_MODE_THIN = 1,
- RADEON_MICRO_MODE_DEPTH = 2,
- RADEON_MICRO_MODE_ROTATED = 3,
-};
-
-/* the first 16 bits are reserved for libdrm_radeon, don't use them */
-#define RADEON_SURF_SCANOUT (1 << 16)
-#define RADEON_SURF_ZBUFFER (1 << 17)
-#define RADEON_SURF_SBUFFER (1 << 18)
-#define RADEON_SURF_Z_OR_SBUFFER (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
-/* bits 19 and 20 are reserved for libdrm_radeon, don't use them */
-#define RADEON_SURF_FMASK (1 << 21)
-#define RADEON_SURF_DISABLE_DCC (1 << 22)
-#define RADEON_SURF_TC_COMPATIBLE_HTILE (1 << 23)
-#define RADEON_SURF_IMPORTED (1 << 24)
-#define RADEON_SURF_OPTIMIZE_FOR_SPACE (1 << 25)
-
-struct radeon_surf_level {
- uint64_t offset;
- uint64_t slice_size;
- uint64_t dcc_offset;
- uint64_t dcc_fast_clear_size;
- uint16_t nblk_x;
- uint16_t nblk_y;
- enum radeon_surf_mode mode;
-};
-
-struct radeon_surf {
- /* Format properties. */
- unsigned blk_w:4;
- unsigned blk_h:4;
- unsigned bpe:5;
- /* Number of mipmap levels where DCC is enabled starting from level 0.
- * Non-zero levels may be disabled due to alignment constraints, but not
- * the first level.
- */
- unsigned num_dcc_levels:4;
- unsigned is_linear:1;
- uint32_t flags;
-
- /* These are return values. Some of them can be set by the caller, but
- * they will be treated as hints (e.g. bankw, bankh) and might be
- * changed by the calculator.
- */
- uint64_t surf_size;
- uint64_t dcc_size;
- uint64_t htile_size;
-
- uint32_t surf_alignment;
- uint32_t dcc_alignment;
- uint32_t htile_alignment;
-
- /* This applies to EG and later. */
- unsigned bankw:4; /* max 8 */
- unsigned bankh:4; /* max 8 */
- unsigned mtilea:4; /* max 8 */
- unsigned tile_split:13; /* max 4K */
- unsigned stencil_tile_split:13; /* max 4K */
- unsigned pipe_config:5; /* max 17 */
- unsigned num_banks:5; /* max 16 */
- unsigned macro_tile_index:4; /* max 15 */
- unsigned micro_tile_mode:3; /* displayable, thin, depth, rotated */
-
- /* Whether the depth miptree or stencil miptree as used by the DB are
- * adjusted from their TC compatible form to ensure depth/stencil
- * compatibility. If either is true, the corresponding plane cannot be
- * sampled from.
- */
- unsigned depth_adjusted:1;
- unsigned stencil_adjusted:1;
-
- struct radeon_surf_level level[RADEON_SURF_MAX_LEVELS];
- struct radeon_surf_level stencil_level[RADEON_SURF_MAX_LEVELS];
- uint8_t tiling_index[RADEON_SURF_MAX_LEVELS];
- uint8_t stencil_tiling_index[RADEON_SURF_MAX_LEVELS];
-};
-
struct radeon_bo_list_item {
uint64_t bo_size;
uint64_t vm_address;
unsigned slice_size,
struct winsys_handle *whandle);
+ /**
+ * Change the commitment of a (64KB-page aligned) region of the given
+ * sparse buffer.
+ *
+ * \warning There is no automatic synchronization with command submission.
+ *
+ * \note Only implemented by the amdgpu winsys.
+ *
+ * \return false on out of memory or other failure, true on success.
+ */
+ bool (*buffer_commit)(struct pb_buffer *buf,
+ uint64_t offset, uint64_t size,
+ bool commit);
+
/**
* Return the virtual address of a buffer.
*