radeonsi: remove Constant Engine support

[mesa.git] / src / gallium / drivers / radeon / radeon_winsys.h

diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h
index 1be94f71e8beacc9ccc36a0d1f5520f41d3e639d..b00b1443e7442846f2a48315b964c535651cddb1 100644 (file)
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -173,8 +173,7 @@ struct radeon_winsys_cs {
     unsigned                      max_prev; /* Space in array pointed to by prev. */
     unsigned                      prev_dw; /* Total number of dwords in previous chunks. */
 
-    /* Memory usage of the buffer list. These are always 0 for CE and preamble
-     * IBs. */
+    /* Memory usage of the buffer list. These are always 0 for preamble IBs. */
     uint64_t                      used_vram;
     uint64_t                      used_gart;
 };
@@ -360,6 +359,9 @@ struct radeon_winsys {
      */
     bool (*buffer_is_user_ptr)(struct pb_buffer *buf);
 
+    /** Whether the buffer was suballocated. */
+    bool (*buffer_is_suballocated)(struct pb_buffer *buf);
+
     /**
      * Get a winsys handle from a winsys buffer. The internal structure
      * of the handle is platform-specific and only a winsys should access it.
@@ -453,36 +455,6 @@ struct radeon_winsys {
                                                        struct pipe_fence_handle **fence),
                                           void *flush_ctx);
 
-    /**
-     * Add a constant engine IB to a graphics CS. This makes the graphics CS
-     * from "cs_create" a group of two IBs that share a buffer list and are
-     * flushed together.
-     *
-     * The returned constant CS is only a stream for writing packets to the new
-     * IB. Calling other winsys functions with it is not allowed, not even
-     * "cs_destroy".
-     *
-     * In order to add buffers and check memory usage, use the graphics CS.
-     * In order to flush it, use the graphics CS, which will flush both IBs.
-     * Destroying the graphics CS will destroy both of them.
-     *
-     * \param cs  The graphics CS from "cs_create" that will hold the buffer
-     *            list and will be used for flushing.
-     */
-    struct radeon_winsys_cs *(*cs_add_const_ib)(struct radeon_winsys_cs *cs);
-
-     /**
-     * Add a constant engine preamble IB to a graphics CS. This add an extra IB
-     * in similar manner to cs_add_const_ib. This should always be called after
-     * cs_add_const_ib.
-     *
-     * The returned IB is a constant engine IB that only gets flushed if the
-     * context changed.
-     *
-     * \param cs  The graphics CS from "cs_create" that will hold the buffer
-     *            list and will be used for flushing.
-     */
-    struct radeon_winsys_cs *(*cs_add_const_preamble_ib)(struct radeon_winsys_cs *cs);
     /**
      * Destroy a command stream.
      *
@@ -658,4 +630,95 @@ static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
     cs->current.cdw += count;
 }
 
+enum radeon_heap {
+    RADEON_HEAP_VRAM_NO_CPU_ACCESS,
+    RADEON_HEAP_VRAM,
+    RADEON_HEAP_VRAM_GTT, /* combined heaps */
+    RADEON_HEAP_GTT_WC,
+    RADEON_HEAP_GTT,
+    RADEON_MAX_SLAB_HEAPS,
+    RADEON_MAX_CACHED_HEAPS = RADEON_MAX_SLAB_HEAPS,
+};
+
+static inline enum radeon_bo_domain radeon_domain_from_heap(enum radeon_heap heap)
+{
+    switch (heap) {
+    case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
+    case RADEON_HEAP_VRAM:
+        return RADEON_DOMAIN_VRAM;
+    case RADEON_HEAP_VRAM_GTT:
+        return RADEON_DOMAIN_VRAM_GTT;
+    case RADEON_HEAP_GTT_WC:
+    case RADEON_HEAP_GTT:
+        return RADEON_DOMAIN_GTT;
+    default:
+        assert(0);
+        return (enum radeon_bo_domain)0;
+    }
+}
+
+static inline unsigned radeon_flags_from_heap(enum radeon_heap heap)
+{
+    switch (heap) {
+    case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
+        return RADEON_FLAG_GTT_WC | RADEON_FLAG_NO_CPU_ACCESS;
+    case RADEON_HEAP_VRAM:
+    case RADEON_HEAP_VRAM_GTT:
+    case RADEON_HEAP_GTT_WC:
+        return RADEON_FLAG_GTT_WC;
+    case RADEON_HEAP_GTT:
+    default:
+        return 0;
+    }
+}
+
+/* The pb cache bucket is chosen to minimize pb_cache misses.
+ * It must be between 0 and 3 inclusive.
+ */
+static inline unsigned radeon_get_pb_cache_bucket_index(enum radeon_heap heap)
+{
+    switch (heap) {
+    case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
+        return 0;
+    case RADEON_HEAP_VRAM:
+    case RADEON_HEAP_VRAM_GTT:
+        return 1;
+    case RADEON_HEAP_GTT_WC:
+        return 2;
+    case RADEON_HEAP_GTT:
+    default:
+        return 3;
+    }
+}
+
+/* Return the heap index for winsys allocators, or -1 on failure. */
+static inline int radeon_get_heap_index(enum radeon_bo_domain domain,
+                                        enum radeon_bo_flag flags)
+{
+    /* VRAM implies WC (write combining) */
+    assert(!(domain & RADEON_DOMAIN_VRAM) || flags & RADEON_FLAG_GTT_WC);
+    /* NO_CPU_ACCESS implies VRAM only. */
+    assert(!(flags & RADEON_FLAG_NO_CPU_ACCESS) || domain == RADEON_DOMAIN_VRAM);
+
+    /* Unsupported flags: NO_SUBALLOC, SPARSE. */
+    if (flags & ~(RADEON_FLAG_GTT_WC | RADEON_FLAG_NO_CPU_ACCESS))
+        return -1;
+
+    switch (domain) {
+    case RADEON_DOMAIN_VRAM:
+        if (flags & RADEON_FLAG_NO_CPU_ACCESS)
+            return RADEON_HEAP_VRAM_NO_CPU_ACCESS;
+        else
+            return RADEON_HEAP_VRAM;
+    case RADEON_DOMAIN_VRAM_GTT:
+        return RADEON_HEAP_VRAM_GTT;
+    case RADEON_DOMAIN_GTT:
+        if (flags & RADEON_FLAG_GTT_WC)
+            return RADEON_HEAP_GTT_WC;
+        else
+            return RADEON_HEAP_GTT;
+    }
+    return -1;
+}
+
 #endif