/*
* Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
- * Copyright 2014,2015 Advanced Micro Devices, Inc.
+ * Copyright 2015 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Jerome Glisse
*/
#include "sid.h"
#include "si_pipe.h"
-#include "radeon/r600_cs.h"
-
-#include "util/u_format.h"
-static void cik_sdma_do_copy_buffer(struct si_context *ctx,
- struct pipe_resource *dst,
- struct pipe_resource *src,
- uint64_t dst_offset,
- uint64_t src_offset,
- uint64_t size)
+static void cik_sdma_copy_buffer(struct si_context *ctx,
+ struct pipe_resource *dst,
+ struct pipe_resource *src,
+ uint64_t dst_offset,
+ uint64_t src_offset,
+ uint64_t size)
{
- struct radeon_winsys_cs *cs = ctx->b.dma.cs;
+ struct radeon_cmdbuf *cs = ctx->dma_cs;
unsigned i, ncopy, csize;
- struct r600_resource *rdst = (struct r600_resource*)dst;
- struct r600_resource *rsrc = (struct r600_resource*)src;
+ struct r600_resource *rdst = r600_resource(dst);
+ struct r600_resource *rsrc = r600_resource(src);
- dst_offset += r600_resource(dst)->gpu_address;
- src_offset += r600_resource(src)->gpu_address;
+ /* Mark the buffer range of destination as valid (initialized),
+ * so that transfer_map knows it should wait for the GPU when mapping
+ * that range. */
+ util_range_add(&rdst->valid_buffer_range, dst_offset,
+ dst_offset + size);
+
+ dst_offset += rdst->gpu_address;
+ src_offset += rsrc->gpu_address;
ncopy = DIV_ROUND_UP(size, CIK_SDMA_COPY_MAX_SIZE);
- r600_need_dma_space(&ctx->b, ncopy * 7, rdst, rsrc);
+ si_need_dma_space(ctx, ncopy * 7, rdst, rsrc);
for (i = 0; i < ncopy; i++) {
csize = MIN2(size, CIK_SDMA_COPY_MAX_SIZE);
radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
CIK_SDMA_COPY_SUB_OPCODE_LINEAR,
0));
- radeon_emit(cs, csize);
+ radeon_emit(cs, ctx->chip_class >= GFX9 ? csize - 1 : csize);
radeon_emit(cs, 0); /* src/dst endian swap */
radeon_emit(cs, src_offset);
radeon_emit(cs, src_offset >> 32);
}
}
-static void cik_sdma_copy_buffer(struct si_context *ctx,
- struct pipe_resource *dst,
- struct pipe_resource *src,
- uint64_t dst_offset,
- uint64_t src_offset,
- uint64_t size)
-{
- struct r600_resource *rdst = (struct r600_resource*)dst;
-
- /* Mark the buffer range of destination as valid (initialized),
- * so that transfer_map knows it should wait for the GPU when mapping
- * that range. */
- util_range_add(&rdst->valid_buffer_range, dst_offset,
- dst_offset + size);
-
- cik_sdma_do_copy_buffer(ctx, dst, src, dst_offset, src_offset, size);
- r600_dma_emit_wait_idle(&ctx->b);
-}
-
static unsigned minify_as_blocks(unsigned width, unsigned level, unsigned blk_w)
{
width = u_minify(width, level);
}
static unsigned encode_tile_info(struct si_context *sctx,
- struct r600_texture *tex, unsigned level,
+ struct si_texture *tex, unsigned level,
bool set_bpp)
{
- struct radeon_info *info = &sctx->screen->b.info;
- unsigned tile_index = tex->surface.tiling_index[level];
- unsigned macro_tile_index = tex->surface.macro_tile_index;
+ struct radeon_info *info = &sctx->screen->info;
+ unsigned tile_index = tex->surface.u.legacy.tiling_index[level];
+ unsigned macro_tile_index = tex->surface.u.legacy.macro_tile_index;
unsigned tile_mode = info->si_tile_mode_array[tile_index];
unsigned macro_tile_mode = info->cik_macrotile_mode_array[macro_tile_index];
(G_009910_ARRAY_MODE(tile_mode) << 3) |
(G_009910_MICRO_TILE_MODE_NEW(tile_mode) << 8) |
/* Non-depth modes don't have TILE_SPLIT set. */
- ((util_logbase2(tex->surface.tile_split >> 6)) << 11) |
+ ((util_logbase2(tex->surface.u.legacy.tile_split >> 6)) << 11) |
(G_009990_BANK_WIDTH(macro_tile_mode) << 15) |
(G_009990_BANK_HEIGHT(macro_tile_mode) << 18) |
(G_009990_NUM_BANKS(macro_tile_mode) << 21) |
unsigned src_level,
const struct pipe_box *src_box)
{
- struct radeon_info *info = &sctx->screen->b.info;
- struct r600_texture *rsrc = (struct r600_texture*)src;
- struct r600_texture *rdst = (struct r600_texture*)dst;
- unsigned bpp = rdst->surface.bpe;
- uint64_t dst_address = rdst->resource.gpu_address +
- rdst->surface.level[dst_level].offset;
- uint64_t src_address = rsrc->resource.gpu_address +
- rsrc->surface.level[src_level].offset;
- unsigned dst_mode = rdst->surface.level[dst_level].mode;
- unsigned src_mode = rsrc->surface.level[src_level].mode;
- unsigned dst_tile_index = rdst->surface.tiling_index[dst_level];
- unsigned src_tile_index = rsrc->surface.tiling_index[src_level];
+ struct radeon_info *info = &sctx->screen->info;
+ struct si_texture *ssrc = (struct si_texture*)src;
+ struct si_texture *sdst = (struct si_texture*)dst;
+ unsigned bpp = sdst->surface.bpe;
+ uint64_t dst_address = sdst->buffer.gpu_address +
+ sdst->surface.u.legacy.level[dst_level].offset;
+ uint64_t src_address = ssrc->buffer.gpu_address +
+ ssrc->surface.u.legacy.level[src_level].offset;
+ unsigned dst_mode = sdst->surface.u.legacy.level[dst_level].mode;
+ unsigned src_mode = ssrc->surface.u.legacy.level[src_level].mode;
+ unsigned dst_tile_index = sdst->surface.u.legacy.tiling_index[dst_level];
+ unsigned src_tile_index = ssrc->surface.u.legacy.tiling_index[src_level];
unsigned dst_tile_mode = info->si_tile_mode_array[dst_tile_index];
unsigned src_tile_mode = info->si_tile_mode_array[src_tile_index];
unsigned dst_micro_mode = G_009910_MICRO_TILE_MODE_NEW(dst_tile_mode);
unsigned src_micro_mode = G_009910_MICRO_TILE_MODE_NEW(src_tile_mode);
- unsigned dst_pitch = rdst->surface.level[dst_level].pitch_bytes / bpp;
- unsigned src_pitch = rsrc->surface.level[src_level].pitch_bytes / bpp;
- uint64_t dst_slice_pitch = rdst->surface.level[dst_level].slice_size / bpp;
- uint64_t src_slice_pitch = rsrc->surface.level[src_level].slice_size / bpp;
- unsigned dst_width = minify_as_blocks(rdst->resource.b.b.width0,
- dst_level, rdst->surface.blk_w);
- unsigned src_width = minify_as_blocks(rsrc->resource.b.b.width0,
- src_level, rsrc->surface.blk_w);
- unsigned dst_height = minify_as_blocks(rdst->resource.b.b.height0,
- dst_level, rdst->surface.blk_h);
- unsigned src_height = minify_as_blocks(rsrc->resource.b.b.height0,
- src_level, rsrc->surface.blk_h);
- unsigned srcx = src_box->x / rsrc->surface.blk_w;
- unsigned srcy = src_box->y / rsrc->surface.blk_h;
+ unsigned dst_tile_swizzle = dst_mode == RADEON_SURF_MODE_2D ?
+ sdst->surface.tile_swizzle : 0;
+ unsigned src_tile_swizzle = src_mode == RADEON_SURF_MODE_2D ?
+ ssrc->surface.tile_swizzle : 0;
+ unsigned dst_pitch = sdst->surface.u.legacy.level[dst_level].nblk_x;
+ unsigned src_pitch = ssrc->surface.u.legacy.level[src_level].nblk_x;
+ uint64_t dst_slice_pitch = ((uint64_t)sdst->surface.u.legacy.level[dst_level].slice_size_dw * 4) / bpp;
+ uint64_t src_slice_pitch = ((uint64_t)ssrc->surface.u.legacy.level[src_level].slice_size_dw * 4) / bpp;
+ unsigned dst_width = minify_as_blocks(sdst->buffer.b.b.width0,
+ dst_level, sdst->surface.blk_w);
+ unsigned src_width = minify_as_blocks(ssrc->buffer.b.b.width0,
+ src_level, ssrc->surface.blk_w);
+ unsigned dst_height = minify_as_blocks(sdst->buffer.b.b.height0,
+ dst_level, sdst->surface.blk_h);
+ unsigned src_height = minify_as_blocks(ssrc->buffer.b.b.height0,
+ src_level, ssrc->surface.blk_h);
+ unsigned srcx = src_box->x / ssrc->surface.blk_w;
+ unsigned srcy = src_box->y / ssrc->surface.blk_h;
unsigned srcz = src_box->z;
- unsigned copy_width = DIV_ROUND_UP(src_box->width, rsrc->surface.blk_w);
- unsigned copy_height = DIV_ROUND_UP(src_box->height, rsrc->surface.blk_h);
+ unsigned copy_width = DIV_ROUND_UP(src_box->width, ssrc->surface.blk_w);
+ unsigned copy_height = DIV_ROUND_UP(src_box->height, ssrc->surface.blk_h);
unsigned copy_depth = src_box->depth;
assert(src_level <= src->last_level);
assert(dst_level <= dst->last_level);
- assert(rdst->surface.level[dst_level].offset +
+ assert(sdst->surface.u.legacy.level[dst_level].offset +
dst_slice_pitch * bpp * (dstz + src_box->depth) <=
- rdst->resource.buf->size);
- assert(rsrc->surface.level[src_level].offset +
+ sdst->buffer.buf->size);
+ assert(ssrc->surface.u.legacy.level[src_level].offset +
src_slice_pitch * bpp * (srcz + src_box->depth) <=
- rsrc->resource.buf->size);
-
- /* Test CIK with radeon and amdgpu before enabling this. */
- if (sctx->b.chip_class == CIK)
- return false;
+ ssrc->buffer.buf->size);
- if (!r600_prepare_for_dma_blit(&sctx->b, rdst, dst_level, dstx, dsty,
- dstz, rsrc, src_level, src_box))
+ if (!si_prepare_for_dma_blit(sctx, sdst, dst_level, dstx, dsty,
+ dstz, ssrc, src_level, src_box))
return false;
- dstx /= rdst->surface.blk_w;
- dsty /= rdst->surface.blk_h;
+ dstx /= sdst->surface.blk_w;
+ dsty /= sdst->surface.blk_h;
if (srcx >= (1 << 14) ||
srcy >= (1 << 14) ||
dstz >= (1 << 11))
return false;
+ dst_address |= dst_tile_swizzle << 8;
+ src_address |= src_tile_swizzle << 8;
+
/* Linear -> linear sub-window copy. */
if (dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED &&
src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED &&
copy_height <= (1 << 14) &&
copy_depth <= (1 << 11) &&
/* HW limitation - CIK: */
- (sctx->b.chip_class != CIK ||
+ (sctx->chip_class != CIK ||
(copy_width < (1 << 14) &&
copy_height < (1 << 14) &&
copy_depth < (1 << 11))) &&
/* HW limitation - some CIK parts: */
- ((sctx->b.family != CHIP_BONAIRE &&
- sctx->b.family != CHIP_KAVERI) ||
+ ((sctx->family != CHIP_BONAIRE &&
+ sctx->family != CHIP_KAVERI) ||
(srcx + copy_width != (1 << 14) &&
srcy + copy_height != (1 << 14)))) {
- struct radeon_winsys_cs *cs = sctx->b.dma.cs;
+ struct radeon_cmdbuf *cs = sctx->dma_cs;
- r600_need_dma_space(&sctx->b, 13, &rdst->resource, &rsrc->resource);
+ si_need_dma_space(sctx, 13, &sdst->buffer, &ssrc->buffer);
radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
CIK_SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW, 0) |
radeon_emit(cs, dstx | (dsty << 16));
radeon_emit(cs, dstz | ((dst_pitch - 1) << 16));
radeon_emit(cs, dst_slice_pitch - 1);
- if (sctx->b.chip_class == CIK) {
+ if (sctx->chip_class == CIK) {
radeon_emit(cs, copy_width | (copy_height << 16));
radeon_emit(cs, copy_depth);
} else {
radeon_emit(cs, (copy_width - 1) | ((copy_height - 1) << 16));
radeon_emit(cs, (copy_depth - 1));
}
-
- r600_dma_emit_wait_idle(&sctx->b);
return true;
}
/* Tiled <-> linear sub-window copy. */
if ((src_mode >= RADEON_SURF_MODE_1D) != (dst_mode >= RADEON_SURF_MODE_1D)) {
- struct r600_texture *tiled = src_mode >= RADEON_SURF_MODE_1D ? rsrc : rdst;
- struct r600_texture *linear = tiled == rsrc ? rdst : rsrc;
- unsigned tiled_level = tiled == rsrc ? src_level : dst_level;
- unsigned linear_level = linear == rsrc ? src_level : dst_level;
- unsigned tiled_x = tiled == rsrc ? srcx : dstx;
- unsigned linear_x = linear == rsrc ? srcx : dstx;
- unsigned tiled_y = tiled == rsrc ? srcy : dsty;
- unsigned linear_y = linear == rsrc ? srcy : dsty;
- unsigned tiled_z = tiled == rsrc ? srcz : dstz;
- unsigned linear_z = linear == rsrc ? srcz : dstz;
- unsigned tiled_width = tiled == rsrc ? src_width : dst_width;
- unsigned linear_width = linear == rsrc ? src_width : dst_width;
- unsigned tiled_pitch = tiled == rsrc ? src_pitch : dst_pitch;
- unsigned linear_pitch = linear == rsrc ? src_pitch : dst_pitch;
- unsigned tiled_slice_pitch = tiled == rsrc ? src_slice_pitch : dst_slice_pitch;
- unsigned linear_slice_pitch = linear == rsrc ? src_slice_pitch : dst_slice_pitch;
- uint64_t tiled_address = tiled == rsrc ? src_address : dst_address;
- uint64_t linear_address = linear == rsrc ? src_address : dst_address;
- unsigned tiled_micro_mode = tiled == rsrc ? src_micro_mode : dst_micro_mode;
+ struct si_texture *tiled = src_mode >= RADEON_SURF_MODE_1D ? ssrc : sdst;
+ struct si_texture *linear = tiled == ssrc ? sdst : ssrc;
+ unsigned tiled_level = tiled == ssrc ? src_level : dst_level;
+ unsigned linear_level = linear == ssrc ? src_level : dst_level;
+ unsigned tiled_x = tiled == ssrc ? srcx : dstx;
+ unsigned linear_x = linear == ssrc ? srcx : dstx;
+ unsigned tiled_y = tiled == ssrc ? srcy : dsty;
+ unsigned linear_y = linear == ssrc ? srcy : dsty;
+ unsigned tiled_z = tiled == ssrc ? srcz : dstz;
+ unsigned linear_z = linear == ssrc ? srcz : dstz;
+ unsigned tiled_width = tiled == ssrc ? src_width : dst_width;
+ unsigned linear_width = linear == ssrc ? src_width : dst_width;
+ unsigned tiled_pitch = tiled == ssrc ? src_pitch : dst_pitch;
+ unsigned linear_pitch = linear == ssrc ? src_pitch : dst_pitch;
+ unsigned tiled_slice_pitch = tiled == ssrc ? src_slice_pitch : dst_slice_pitch;
+ unsigned linear_slice_pitch = linear == ssrc ? src_slice_pitch : dst_slice_pitch;
+ uint64_t tiled_address = tiled == ssrc ? src_address : dst_address;
+ uint64_t linear_address = linear == ssrc ? src_address : dst_address;
+ unsigned tiled_micro_mode = tiled == ssrc ? src_micro_mode : dst_micro_mode;
assert(tiled_pitch % 8 == 0);
assert(tiled_slice_pitch % 64 == 0);
copy_width_aligned = align(copy_width, xalign);
/* HW limitations. */
- if ((sctx->b.family == CHIP_BONAIRE ||
- sctx->b.family == CHIP_KAVERI) &&
+ if ((sctx->family == CHIP_BONAIRE ||
+ sctx->family == CHIP_KAVERI) &&
linear_pitch - 1 == 0x3fff &&
bpp == 16)
return false;
- if (sctx->b.chip_class == CIK &&
+ if (sctx->chip_class == CIK &&
(copy_width_aligned == (1 << 14) ||
copy_height == (1 << 14) ||
copy_depth == (1 << 11)))
return false;
- if ((sctx->b.family == CHIP_BONAIRE ||
- sctx->b.family == CHIP_KAVERI ||
- sctx->b.family == CHIP_KABINI ||
- sctx->b.family == CHIP_MULLINS) &&
+ if ((sctx->family == CHIP_BONAIRE ||
+ sctx->family == CHIP_KAVERI ||
+ sctx->family == CHIP_KABINI ||
+ sctx->family == CHIP_MULLINS) &&
(tiled_x + copy_width == (1 << 14) ||
tiled_y + copy_height == (1 << 14)))
return false;
* starts reading from an address preceding linear_address!!!
*/
start_linear_address =
- linear->surface.level[linear_level].offset +
+ linear->surface.u.legacy.level[linear_level].offset +
bpp * (linear_z * linear_slice_pitch +
linear_y * linear_pitch +
linear_x);
start_linear_address -= (int)(bpp * (tiled_x % granularity));
end_linear_address =
- linear->surface.level[linear_level].offset +
+ linear->surface.u.legacy.level[linear_level].offset +
bpp * ((linear_z + copy_depth - 1) * linear_slice_pitch +
(linear_y + copy_height - 1) * linear_pitch +
(linear_x + copy_width));
(tiled_x + copy_width) % granularity;
if (start_linear_address < 0 ||
- end_linear_address > linear->surface.bo_size)
+ end_linear_address > linear->surface.surf_size)
return false;
/* Check requirements. */
copy_width_aligned % xalign == 0 &&
tiled_micro_mode != V_009910_ADDR_SURF_ROTATED_MICRO_TILING &&
/* check if everything fits into the bitfields */
- tiled->surface.tile_split <= 4096 &&
+ tiled->surface.u.legacy.tile_split <= 4096 &&
pitch_tile_max < (1 << 11) &&
slice_tile_max < (1 << 22) &&
linear_pitch <= (1 << 14) &&
copy_width_aligned <= (1 << 14) &&
copy_height <= (1 << 14) &&
copy_depth <= (1 << 11)) {
- struct radeon_winsys_cs *cs = sctx->b.dma.cs;
- uint32_t direction = linear == rdst ? 1u << 31 : 0;
+ struct radeon_cmdbuf *cs = sctx->dma_cs;
+ uint32_t direction = linear == sdst ? 1u << 31 : 0;
- r600_need_dma_space(&sctx->b, 14, &rdst->resource, &rsrc->resource);
+ si_need_dma_space(sctx, 14, &sdst->buffer, &ssrc->buffer);
radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
CIK_SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW, 0) |
radeon_emit(cs, linear_x | (linear_y << 16));
radeon_emit(cs, linear_z | ((linear_pitch - 1) << 16));
radeon_emit(cs, linear_slice_pitch - 1);
- if (sctx->b.chip_class == CIK) {
+ if (sctx->chip_class == CIK) {
radeon_emit(cs, copy_width_aligned | (copy_height << 16));
radeon_emit(cs, copy_depth);
} else {
radeon_emit(cs, (copy_width_aligned - 1) | ((copy_height - 1) << 16));
radeon_emit(cs, (copy_depth - 1));
}
-
- r600_dma_emit_wait_idle(&sctx->b);
return true;
}
}
/* check if these fit into the bitfields */
src_address % 256 == 0 &&
dst_address % 256 == 0 &&
- rsrc->surface.tile_split <= 4096 &&
- rdst->surface.tile_split <= 4096 &&
+ ssrc->surface.u.legacy.tile_split <= 4096 &&
+ sdst->surface.u.legacy.tile_split <= 4096 &&
dstx % 8 == 0 &&
dsty % 8 == 0 &&
srcx % 8 == 0 &&
srcy % 8 == 0 &&
- /* this can either be equal, or display->rotated (VI only) */
+ /* this can either be equal, or display->rotated (VI+ only) */
(src_micro_mode == dst_micro_mode ||
- (sctx->b.chip_class == VI &&
+ (sctx->chip_class >= VI &&
src_micro_mode == V_009910_ADDR_SURF_DISPLAY_MICRO_TILING &&
dst_micro_mode == V_009910_ADDR_SURF_ROTATED_MICRO_TILING))) {
assert(src_pitch % 8 == 0);
copy_width_aligned % 8 == 0 &&
copy_height_aligned % 8 == 0 &&
/* HW limitation - CIK: */
- (sctx->b.chip_class != CIK ||
+ (sctx->chip_class != CIK ||
(copy_width_aligned < (1 << 14) &&
copy_height_aligned < (1 << 14) &&
copy_depth < (1 << 11))) &&
/* HW limitation - some CIK parts: */
- ((sctx->b.family != CHIP_BONAIRE &&
- sctx->b.family != CHIP_KAVERI &&
- sctx->b.family != CHIP_KABINI &&
- sctx->b.family != CHIP_MULLINS) ||
+ ((sctx->family != CHIP_BONAIRE &&
+ sctx->family != CHIP_KAVERI &&
+ sctx->family != CHIP_KABINI &&
+ sctx->family != CHIP_MULLINS) ||
(srcx + copy_width_aligned != (1 << 14) &&
srcy + copy_height_aligned != (1 << 14) &&
dstx + copy_width != (1 << 14)))) {
- struct radeon_winsys_cs *cs = sctx->b.dma.cs;
+ struct radeon_cmdbuf *cs = sctx->dma_cs;
- r600_need_dma_space(&sctx->b, 15, &rdst->resource, &rsrc->resource);
+ si_need_dma_space(sctx, 15, &sdst->buffer, &ssrc->buffer);
radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
CIK_SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW, 0));
radeon_emit(cs, srcx | (srcy << 16));
radeon_emit(cs, srcz | (src_pitch_tile_max << 16));
radeon_emit(cs, src_slice_tile_max);
- radeon_emit(cs, encode_tile_info(sctx, rsrc, src_level, true));
+ radeon_emit(cs, encode_tile_info(sctx, ssrc, src_level, true));
radeon_emit(cs, dst_address);
radeon_emit(cs, dst_address >> 32);
radeon_emit(cs, dstx | (dsty << 16));
radeon_emit(cs, dstz | (dst_pitch_tile_max << 16));
radeon_emit(cs, dst_slice_tile_max);
- radeon_emit(cs, encode_tile_info(sctx, rdst, dst_level, false));
- if (sctx->b.chip_class == CIK) {
+ radeon_emit(cs, encode_tile_info(sctx, sdst, dst_level, false));
+ if (sctx->chip_class == CIK) {
radeon_emit(cs, copy_width_aligned |
(copy_height_aligned << 16));
radeon_emit(cs, copy_depth);
((copy_height_aligned - 8) << 16));
radeon_emit(cs, (copy_depth - 1));
}
-
- r600_dma_emit_wait_idle(&sctx->b);
return true;
}
}
{
struct si_context *sctx = (struct si_context *)ctx;
- if (!sctx->b.dma.cs)
+ if (!sctx->dma_cs ||
+ src->flags & PIPE_RESOURCE_FLAG_SPARSE ||
+ dst->flags & PIPE_RESOURCE_FLAG_SPARSE)
goto fallback;
if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
return;
}
- /* Carrizo SDMA texture copying is very broken for some users.
- * https://bugs.freedesktop.org/show_bug.cgi?id=97029
- */
- if (sctx->b.family == CHIP_CARRIZO)
- goto fallback;
-
- if (cik_sdma_copy_texture(sctx, dst, dst_level, dstx, dsty, dstz,
+ if ((sctx->chip_class == CIK || sctx->chip_class == VI) &&
+ cik_sdma_copy_texture(sctx, dst, dst_level, dstx, dsty, dstz,
src, src_level, src_box))
return;
void cik_init_sdma_functions(struct si_context *sctx)
{
- sctx->b.dma_copy = cik_sdma_copy;
+ sctx->dma_copy = cik_sdma_copy;
}