radeonsi: Set PIPE_SHADER_CAP_MAX_SHADER_IMAGES
[mesa.git] / src / gallium / drivers / radeonsi / cik_sdma.c
index 2de237b47163fd6f1fc77ffd777226c1ded0f315..6eb62dcc8903195e53e66597e7bfc6cb13d0951a 100644 (file)
@@ -196,7 +196,7 @@ static void cik_sdma_copy_tile(struct si_context *ctx,
                        (tile_split << 11) | (mt << 8) | (array_mode << 3) |
                        lbpe;
                cs->buf[cs->cdw++] = y << 16; /* | x */
-               cs->buf[cs->cdw++] = 0; /* z */;
+               cs->buf[cs->cdw++] = 0; /* z */
                cs->buf[cs->cdw++] = addr & 0xfffffffc;
                cs->buf[cs->cdw++] = addr >> 32;
                cs->buf[cs->cdw++] = (pitch / bpe) - 1;
@@ -243,7 +243,7 @@ void cik_sdma_copy(struct pipe_context *ctx,
        if (src->format != dst->format ||
            rdst->surface.nsamples > 1 || rsrc->surface.nsamples > 1 ||
            (rdst->dirty_level_mask | rdst->stencil_dirty_level_mask) & (1 << dst_level) ||
-           rdst->dcc_buffer || rsrc->dcc_buffer) {
+           rdst->dcc_offset || rsrc->dcc_offset) {
                goto fallback;
        }
 
@@ -308,7 +308,7 @@ void cik_sdma_copy(struct pipe_context *ctx,
                        }
 
                        mtilew = (8 * rsrc->surface.bankw *
-                                 sctx->screen->b.tiling_info.num_channels) *
+                                 sctx->screen->b.info.num_tile_pipes) *
                                rsrc->surface.mtilea;
                        assert(!(mtilew & (mtilew - 1)));
                        mtileh = (8 * rsrc->surface.bankh * num_banks) /