#include "util/u_memory.h"
#include <errno.h>
-#define GROUP_FORCE_NEW_BLOCK 0
-
-static const struct r600_reg si_config_reg_list[] = {
- {R_0088B0_VGT_VTX_VECT_EJECT_REG, REG_FLAG_FLUSH_CHANGE},
- {R_0088C8_VGT_ESGS_RING_SIZE, REG_FLAG_FLUSH_CHANGE},
- {R_0088CC_VGT_GSVS_RING_SIZE, REG_FLAG_FLUSH_CHANGE},
- {R_008A14_PA_CL_ENHANCE, REG_FLAG_FLUSH_CHANGE},
- {R_009100_SPI_CONFIG_CNTL, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE},
- {R_00913C_SPI_CONFIG_CNTL_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE},
-};
-
-static const struct r600_reg si_context_reg_list[] = {
- {R_028004_DB_COUNT_CONTROL, 0},
- {R_028010_DB_RENDER_OVERRIDE2, 0},
- {GROUP_FORCE_NEW_BLOCK, 0},
- {R_028014_DB_HTILE_DATA_BASE, REG_FLAG_NEED_BO},
- {GROUP_FORCE_NEW_BLOCK, 0},
- {R_028080_TA_BC_BASE_ADDR, REG_FLAG_NEED_BO},
- {GROUP_FORCE_NEW_BLOCK, 0},
- {R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0},
- {GROUP_FORCE_NEW_BLOCK, 0},
- {R_0286C4_SPI_VS_OUT_CONFIG, 0},
- {R_0286CC_SPI_PS_INPUT_ENA, 0},
- {R_0286D0_SPI_PS_INPUT_ADDR, 0},
- {R_0286D8_SPI_PS_IN_CONTROL, 0},
- {R_0286E0_SPI_BARYC_CNTL, 0},
- {R_02870C_SPI_SHADER_POS_FORMAT, 0},
- {R_028710_SPI_SHADER_Z_FORMAT, 0},
- {R_028714_SPI_SHADER_COL_FORMAT, 0},
- {R_0287D4_PA_CL_POINT_X_RAD, 0},
- {R_0287D8_PA_CL_POINT_Y_RAD, 0},
- {R_0287DC_PA_CL_POINT_SIZE, 0},
- {R_0287E0_PA_CL_POINT_CULL_RAD, 0},
- {R_028804_DB_EQAA, 0},
- {R_02880C_DB_SHADER_CONTROL, 0},
- {R_028824_PA_SU_LINE_STIPPLE_CNTL, 0},
- {R_028828_PA_SU_LINE_STIPPLE_SCALE, 0},
- {R_02882C_PA_SU_PRIM_FILTER_CNTL, 0},
- {R_028A10_VGT_OUTPUT_PATH_CNTL, 0},
- {R_028A14_VGT_HOS_CNTL, 0},
- {R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0},
- {R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0},
- {R_028A20_VGT_HOS_REUSE_DEPTH, 0},
- {R_028A24_VGT_GROUP_PRIM_TYPE, 0},
- {R_028A28_VGT_GROUP_FIRST_DECR, 0},
- {R_028A2C_VGT_GROUP_DECR, 0},
- {R_028A30_VGT_GROUP_VECT_0_CNTL, 0},
- {R_028A34_VGT_GROUP_VECT_1_CNTL, 0},
- {R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0},
- {R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0},
- {R_028A40_VGT_GS_MODE, 0},
- {R_028A4C_PA_SC_MODE_CNTL_1, 0},
- {R_028A50_VGT_ENHANCE, 0},
- {R_028A54_VGT_GS_PER_ES, 0},
- {R_028A58_VGT_ES_PER_GS, 0},
- {R_028A5C_VGT_GS_PER_VS, 0},
- {R_028A60_VGT_GSVS_RING_OFFSET_1, 0},
- {R_028A64_VGT_GSVS_RING_OFFSET_2, 0},
- {R_028A68_VGT_GSVS_RING_OFFSET_3, 0},
- {R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0},
- {R_028A70_IA_ENHANCE, 0},
- {R_028A84_VGT_PRIMITIVEID_EN, 0},
- {R_028A8C_VGT_PRIMITIVEID_RESET, 0},
- {R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0},
- {R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0},
- {R_028AA8_IA_MULTI_VGT_PARAM, 0},
- {R_028AAC_VGT_ESGS_RING_ITEMSIZE, 0},
- {R_028AB0_VGT_GSVS_RING_ITEMSIZE, 0},
- {R_028AB4_VGT_REUSE_OFF, 0},
- {R_028AB8_VGT_VTX_CNT_EN, 0},
- {R_028ABC_DB_HTILE_SURFACE, 0},
- {R_028B54_VGT_SHADER_STAGES_EN, 0},
- {R_028B94_VGT_STRMOUT_CONFIG, 0},
- {R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0},
- {R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0},
- {R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0},
- {R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0},
- {R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, 0},
- {R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, 0},
- {R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, 0},
- {R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0},
- {R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, 0},
- {R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, 0},
- {R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, 0},
- {R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0},
- {R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, 0},
- {R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, 0},
- {R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, 0},
- {R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0},
- {R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, 0},
- {R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2, 0},
- {R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3, 0},
-};
-
-static const struct r600_reg si_sh_reg_list[] = {
- {R_00B020_SPI_SHADER_PGM_LO_PS, REG_FLAG_NEED_BO},
- {R_00B024_SPI_SHADER_PGM_HI_PS, REG_FLAG_NEED_BO},
- {R_00B028_SPI_SHADER_PGM_RSRC1_PS, 0},
- {R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 0},
- {GROUP_FORCE_NEW_BLOCK, 0},
- {R_00B030_SPI_SHADER_USER_DATA_PS_0, REG_FLAG_NEED_BO},
- {R_00B034_SPI_SHADER_USER_DATA_PS_1, 0},
- {GROUP_FORCE_NEW_BLOCK, 0},
- {R_00B038_SPI_SHADER_USER_DATA_PS_2, REG_FLAG_NEED_BO},
- {R_00B03C_SPI_SHADER_USER_DATA_PS_3, 0},
- {GROUP_FORCE_NEW_BLOCK, 0},
- {R_00B040_SPI_SHADER_USER_DATA_PS_4, REG_FLAG_NEED_BO},
- {R_00B044_SPI_SHADER_USER_DATA_PS_5, 0},
- {GROUP_FORCE_NEW_BLOCK, 0},
- {R_00B048_SPI_SHADER_USER_DATA_PS_6, REG_FLAG_NEED_BO},
- {R_00B04C_SPI_SHADER_USER_DATA_PS_7, 0},
- {GROUP_FORCE_NEW_BLOCK, 0},
- {R_00B050_SPI_SHADER_USER_DATA_PS_8, REG_FLAG_NEED_BO},
- {R_00B054_SPI_SHADER_USER_DATA_PS_9, 0},
- {GROUP_FORCE_NEW_BLOCK, 0},
- {R_00B058_SPI_SHADER_USER_DATA_PS_10, REG_FLAG_NEED_BO},
- {R_00B05C_SPI_SHADER_USER_DATA_PS_11, 0},
- {GROUP_FORCE_NEW_BLOCK, 0},
- {R_00B060_SPI_SHADER_USER_DATA_PS_12, REG_FLAG_NEED_BO},
- {R_00B064_SPI_SHADER_USER_DATA_PS_13, 0},
- {GROUP_FORCE_NEW_BLOCK, 0},
- {R_00B068_SPI_SHADER_USER_DATA_PS_14, REG_FLAG_NEED_BO},
- {R_00B06C_SPI_SHADER_USER_DATA_PS_15, 0},
- {GROUP_FORCE_NEW_BLOCK, 0},
- {R_00B120_SPI_SHADER_PGM_LO_VS, REG_FLAG_NEED_BO},
- {R_00B124_SPI_SHADER_PGM_HI_VS, REG_FLAG_NEED_BO},
- {R_00B128_SPI_SHADER_PGM_RSRC1_VS, 0},
- {R_00B12C_SPI_SHADER_PGM_RSRC2_VS, 0},
- {GROUP_FORCE_NEW_BLOCK, 0},
- {R_00B130_SPI_SHADER_USER_DATA_VS_0, REG_FLAG_NEED_BO},
- {R_00B134_SPI_SHADER_USER_DATA_VS_1, 0},
- {GROUP_FORCE_NEW_BLOCK, 0},
- {R_00B138_SPI_SHADER_USER_DATA_VS_2, REG_FLAG_NEED_BO},
- {R_00B13C_SPI_SHADER_USER_DATA_VS_3, 0},
- {GROUP_FORCE_NEW_BLOCK, 0},
- {R_00B140_SPI_SHADER_USER_DATA_VS_4, REG_FLAG_NEED_BO},
- {R_00B144_SPI_SHADER_USER_DATA_VS_5, 0},
- {GROUP_FORCE_NEW_BLOCK, 0},
- {R_00B148_SPI_SHADER_USER_DATA_VS_6, REG_FLAG_NEED_BO},
- {R_00B14C_SPI_SHADER_USER_DATA_VS_7, 0},
- {GROUP_FORCE_NEW_BLOCK, 0},
- {R_00B150_SPI_SHADER_USER_DATA_VS_8, REG_FLAG_NEED_BO},
- {R_00B154_SPI_SHADER_USER_DATA_VS_9, 0},
- {GROUP_FORCE_NEW_BLOCK, 0},
- {R_00B158_SPI_SHADER_USER_DATA_VS_10, REG_FLAG_NEED_BO},
- {R_00B15C_SPI_SHADER_USER_DATA_VS_11, 0},
- {GROUP_FORCE_NEW_BLOCK, 0},
- {R_00B160_SPI_SHADER_USER_DATA_VS_12, REG_FLAG_NEED_BO},
- {R_00B164_SPI_SHADER_USER_DATA_VS_13, 0},
- {GROUP_FORCE_NEW_BLOCK, 0},
- {R_00B168_SPI_SHADER_USER_DATA_VS_14, REG_FLAG_NEED_BO},
- {R_00B16C_SPI_SHADER_USER_DATA_VS_15, 0},
-};
-
int si_context_init(struct r600_context *ctx)
{
int r;
LIST_INITHEAD(&ctx->active_query_list);
- /* init dirty list */
- LIST_INITHEAD(&ctx->dirty);
- LIST_INITHEAD(&ctx->enable_list);
-
- ctx->range = calloc(NUM_RANGES, sizeof(struct r600_range));
- if (!ctx->range) {
- r = -ENOMEM;
- goto out_err;
- }
-
- /* add blocks */
- r = r600_context_add_block(ctx, si_config_reg_list,
- Elements(si_config_reg_list), PKT3_SET_CONFIG_REG, SI_CONFIG_REG_OFFSET);
- if (r)
- goto out_err;
- r = r600_context_add_block(ctx, si_context_reg_list,
- Elements(si_context_reg_list), PKT3_SET_CONTEXT_REG, SI_CONTEXT_REG_OFFSET);
- if (r)
- goto out_err;
- r = r600_context_add_block(ctx, si_sh_reg_list,
- Elements(si_sh_reg_list), PKT3_SET_SH_REG, SI_SH_REG_OFFSET);
- if (r)
- goto out_err;
-
-
- /* PS SAMPLER */
- /* VS SAMPLER */
-
- /* PS SAMPLER BORDER */
- /* VS SAMPLER BORDER */
-
- /* PS RESOURCES */
- /* VS RESOURCES */
-
ctx->cs = ctx->ws->cs_create(ctx->ws);
r600_init_cs(ctx);
ctx->max_db = 8;
return 0;
-out_err:
- r600_context_fini(ctx);
- return r;
}
static inline void evergreen_context_ps_partial_flush(struct r600_context *ctx)
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