util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
switch (uc.ui) {
- case 0x000000FF: /* opaque black */
- border_color_type = 0;
+ case 0x000000FF:
+ border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
break;
- case 0x00000000: /* transparent black */
- border_color_type = 1;
+ case 0x00000000:
+ border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
break;
- case 0xFFFFFFFF: /* white */
- border_color_type = 2;
+ case 0xFFFFFFFF:
+ border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
break;
default: /* Use border color pointer */
- border_color_type = 3;
+ border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
}
rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
aniso_flag_offset << 16 | /* XXX */
- S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
- S_008F30_FILTER_MODE(si_tex_mipfilter(state->min_mip_filter)));
+ S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter)) |
- S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter)));
+ S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter)) |
+ S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
#if 0
bo = (struct r600_resource*)
pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE,
count * sizeof(resource[0]->state));
- ptr = rctx->ws->buffer_map(bo->buf, rctx->cs, PIPE_TRANSFER_WRITE);
+ ptr = rctx->ws->buffer_map(bo->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
for (i = 0; i < count; i++, ptr += sizeof(resource[0]->state)) {
pipe_sampler_view_reference(
memset(ptr, 0, sizeof(resource[0]->state));
}
- rctx->ws->buffer_unmap(bo->buf);
+ rctx->ws->buffer_unmap(bo->cs_buf);
for (i = count; i < NUM_TEX_UNITS; i++) {
if (rctx->ps_samplers.views[i])
bo = (struct r600_resource*)
pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE,
count * sizeof(rstates[0]->val));
- ptr = rctx->ws->buffer_map(bo->buf, rctx->cs, PIPE_TRANSFER_WRITE);
+ ptr = rctx->ws->buffer_map(bo->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
for (i = 0; i < count; i++, ptr += sizeof(rstates[0]->val)) {
memcpy(ptr, rstates[i]->val, sizeof(rstates[0]->val));
}
- rctx->ws->buffer_unmap(bo->buf);
+ rctx->ws->buffer_unmap(bo->cs_buf);
va = r600_resource_va(ctx->screen, (void *)bo);
r600_pipe_state_add_reg(rstate, R_00B038_SPI_SHADER_USER_DATA_PS_2, va, bo, RADEON_USAGE_READ);
format = si_translate_colorformat(surf->base.format);
swap = si_translate_colorswap(surf->base.format);
- if (rtex->resource.b.b.b.usage == PIPE_USAGE_STAGING) {
+ if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
endian = V_028C70_ENDIAN_NONE;
} else {
endian = si_colorformat_endian_swap(format);
struct r600_pipe_state *rstate = &shader->rstate;
struct r600_shader *rshader = &shader->shader;
unsigned i, exports_ps, num_cout, spi_ps_in_control, db_shader_control;
+ unsigned num_sgprs, num_user_sgprs;
int pos_index = -1, face_index = -1;
int ninterp = 0;
boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
va >> 40,
shader->bo, RADEON_USAGE_READ);
+ num_user_sgprs = 6;
+ num_sgprs = shader->num_sgprs;
+ if (num_user_sgprs > num_sgprs)
+ num_sgprs = num_user_sgprs;
/* Last 2 reserved SGPRs are used for VCC */
- /* XXX: Hard-coding 2 SGPRs for constant buffer */
+ num_sgprs += 2;
+ assert(num_sgprs <= 104);
+
r600_pipe_state_add_reg(rstate,
R_00B028_SPI_SHADER_PGM_RSRC1_PS,
- S_00B028_VGPRS(shader->num_vgprs / 4) |
- S_00B028_SGPRS((shader->num_sgprs + 2 + 2 + 1) / 8),
+ S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
+ S_00B028_SGPRS((num_sgprs - 1) / 8),
NULL, 0);
r600_pipe_state_add_reg(rstate,
R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
- S_00B02C_USER_SGPR(6),
+ S_00B02C_USER_SGPR(num_user_sgprs),
NULL, 0);
r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL,
struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_pipe_state *rstate = &shader->rstate;
struct r600_shader *rshader = &shader->shader;
+ unsigned num_sgprs, num_user_sgprs;
unsigned nparams, i;
uint64_t va;
va >> 40,
shader->bo, RADEON_USAGE_READ);
+ num_user_sgprs = 8;
+ num_sgprs = shader->num_sgprs;
+ if (num_user_sgprs > num_sgprs)
+ num_sgprs = num_user_sgprs;
/* Last 2 reserved SGPRs are used for VCC */
- /* XXX: Hard-coding 2 SGPRs for constant buffer */
+ num_sgprs += 2;
+ assert(num_sgprs <= 104);
+
r600_pipe_state_add_reg(rstate,
R_00B128_SPI_SHADER_PGM_RSRC1_VS,
- S_00B128_VGPRS(shader->num_vgprs / 4) |
- S_00B128_SGPRS((shader->num_sgprs + 2 + 2 + 2) / 8),
+ S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
+ S_00B128_SGPRS((num_sgprs - 1) / 8),
NULL, 0);
r600_pipe_state_add_reg(rstate,
R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
- S_00B12C_USER_SGPR(2 + 2),
+ S_00B12C_USER_SGPR(num_user_sgprs),
NULL, 0);
}