radeonsi: add llvm processor names for CIK

[mesa.git] / src / gallium / drivers / radeonsi / r600_resource.h

diff --git a/src/gallium/drivers/radeonsi/r600_resource.h b/src/gallium/drivers/radeonsi/r600_resource.h
index e539eedc3b52ed0e35bc595f664dbced0fa34f22..f7b60ed33bafc78d8c4520296108a2b557f41584 100644 (file)
--- a/src/gallium/drivers/radeonsi/r600_resource.h
+++ b/src/gallium/drivers/radeonsi/r600_resource.h
@@ -26,7 +26,8 @@
 #include "util/u_transfer.h"
 
 /* flag to indicate a resource is to be used as a transfer so should not be tiled */
-#define R600_RESOURCE_FLAG_TRANSFER     PIPE_RESOURCE_FLAG_DRV_PRIV
+#define R600_RESOURCE_FLAG_TRANSFER            PIPE_RESOURCE_FLAG_DRV_PRIV
+#define R600_RESOURCE_FLAG_FLUSHED_DEPTH       (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
 
 /* Texture transfer. */
 struct r600_transfer {
@@ -35,7 +36,7 @@ struct r600_transfer {
        /* Buffer transfer. */
        struct pipe_transfer            *buffer_transfer;
        unsigned                        offset;
-       struct pipe_resource            *staging_texture;
+       struct pipe_resource            *staging;
 };
 
 struct r600_resource_texture {
@@ -46,25 +47,16 @@ struct r600_resource_texture {
         * for the stencil buffer below. */
        enum pipe_format                real_format;
 
-       unsigned                        offset[PIPE_MAX_TEXTURE_LEVELS];
-       unsigned                        pitch_in_bytes[PIPE_MAX_TEXTURE_LEVELS];  /* transfer */
-       unsigned                        pitch_in_blocks[PIPE_MAX_TEXTURE_LEVELS]; /* texture resource */
-       unsigned                        layer_size[PIPE_MAX_TEXTURE_LEVELS];
-       unsigned                        array_mode[PIPE_MAX_TEXTURE_LEVELS];
        unsigned                        pitch_override;
-       unsigned                        size;
-       unsigned                        depth;
-       unsigned                        dirty_db;
+       unsigned                        is_depth;
+       unsigned                        dirty_db_mask; /* each bit says if that miplevel is dirty */
        struct r600_resource_texture    *flushed_depth_texture;
        boolean                         is_flushing_texture;
        struct radeon_surface           surface;
 };
 
-#define R600_TEX_IS_TILED(tex, level) ((tex)->array_mode[level] != V_009910_ARRAY_LINEAR_GENERAL && (tex)->array_mode[level] != V_009910_ARRAY_LINEAR_ALIGNED)
-
 struct r600_surface {
        struct pipe_surface             base;
-       unsigned                        aligned_height;
 };
 
 void r600_init_screen_resource_functions(struct pipe_screen *screen);
@@ -76,7 +68,9 @@ struct pipe_resource *si_texture_from_handle(struct pipe_screen *screen,
                                             const struct pipe_resource *base,
                                             struct winsys_handle *whandle);
 
-int r600_texture_depth_flush(struct pipe_context *ctx, struct pipe_resource *texture, boolean just_create);
+bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
+                                    struct pipe_resource *texture,
+                                    struct r600_resource_texture **staging);
 
 
 struct r600_context;