struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
struct pipe_resource *texture = transfer->resource;
- ctx->resource_copy_region(ctx, rtransfer->staging_texture,
+ ctx->resource_copy_region(ctx, rtransfer->staging,
0, 0, 0, 0, texture, transfer->level,
&transfer->box);
}
sbox.depth = 1;
ctx->resource_copy_region(ctx, texture, transfer->level,
transfer->box.x, transfer->box.y, transfer->box.z,
- rtransfer->staging_texture,
+ rtransfer->staging,
0, &sbox);
}
-unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
+static unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
unsigned level, unsigned layer)
{
- unsigned offset = rtex->offset[level];
-
- switch (rtex->resource.b.b.target) {
- case PIPE_TEXTURE_3D:
- case PIPE_TEXTURE_CUBE:
- default:
- return offset + layer * rtex->layer_size[level];
- }
+ return rtex->surface.level[level].offset +
+ layer * rtex->surface.level[level].slice_size;
}
-static unsigned r600_get_block_alignment(struct pipe_screen *screen,
- enum pipe_format format,
- unsigned array_mode)
+static int r600_init_surface(struct r600_screen *rscreen,
+ struct radeon_surface *surface,
+ const struct pipe_resource *ptex,
+ unsigned array_mode,
+ bool is_flushed_depth)
{
- struct r600_screen* rscreen = (struct r600_screen *)screen;
- unsigned pixsize = util_format_get_blocksize(format);
- int p_align;
-
- switch(array_mode) {
-#if 0
- case V_038000_ARRAY_1D_TILED_THIN1:
- p_align = MAX2(8,
- ((rscreen->tiling_info.group_bytes / 8 / pixsize)));
+ const struct util_format_description *desc =
+ util_format_description(ptex->format);
+ bool is_depth, is_stencil;
+
+ is_depth = util_format_has_depth(desc);
+ is_stencil = util_format_has_stencil(desc);
+
+ surface->npix_x = ptex->width0;
+ surface->npix_y = ptex->height0;
+ surface->npix_z = ptex->depth0;
+ surface->blk_w = util_format_get_blockwidth(ptex->format);
+ surface->blk_h = util_format_get_blockheight(ptex->format);
+ surface->blk_d = 1;
+ surface->array_size = 1;
+ surface->last_level = ptex->last_level;
+
+ if (!is_flushed_depth &&
+ ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
+ surface->bpe = 4; /* stencil is allocated separately on evergreen */
+ } else {
+ surface->bpe = util_format_get_blocksize(ptex->format);
+ /* align byte per element on dword */
+ if (surface->bpe == 3) {
+ surface->bpe = 4;
+ }
+ }
+
+ surface->nsamples = 1;
+ surface->flags = 0;
+ switch (array_mode) {
+ case V_009910_ARRAY_1D_TILED_THIN1:
+ surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
break;
- case V_038000_ARRAY_2D_TILED_THIN1:
- p_align = MAX2(rscreen->tiling_info.num_banks,
- (((rscreen->tiling_info.group_bytes / 8 / pixsize)) *
- rscreen->tiling_info.num_banks)) * 8;
+ case V_009910_ARRAY_2D_TILED_THIN1:
+ surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
break;
- case V_038000_ARRAY_LINEAR_ALIGNED:
- p_align = MAX2(64, rscreen->tiling_info.group_bytes / pixsize);
+ case V_009910_ARRAY_LINEAR_ALIGNED:
+ surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
break;
- case V_038000_ARRAY_LINEAR_GENERAL:
-#endif
+ case V_009910_ARRAY_LINEAR_GENERAL:
default:
- p_align = rscreen->tiling_info.group_bytes / pixsize;
+ surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE);
break;
}
- return p_align;
-}
-
-static unsigned r600_get_height_alignment(struct pipe_screen *screen,
- unsigned array_mode)
-{
- struct r600_screen* rscreen = (struct r600_screen *)screen;
- int h_align;
-
- switch (array_mode) {
-#if 0
- case V_038000_ARRAY_2D_TILED_THIN1:
- h_align = rscreen->tiling_info.num_channels * 8;
+ switch (ptex->target) {
+ case PIPE_TEXTURE_1D:
+ surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
break;
- case V_038000_ARRAY_1D_TILED_THIN1:
- case V_038000_ARRAY_LINEAR_ALIGNED:
- h_align = 8;
+ case PIPE_TEXTURE_RECT:
+ case PIPE_TEXTURE_2D:
+ surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
break;
- case V_038000_ARRAY_LINEAR_GENERAL:
-#endif
- default:
- h_align = 1;
+ case PIPE_TEXTURE_3D:
+ surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
break;
+ case PIPE_TEXTURE_1D_ARRAY:
+ surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
+ surface->array_size = ptex->array_size;
+ break;
+ case PIPE_TEXTURE_2D_ARRAY:
+ surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
+ surface->array_size = ptex->array_size;
+ break;
+ case PIPE_TEXTURE_CUBE:
+ surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
+ break;
+ case PIPE_BUFFER:
+ default:
+ return -EINVAL;
+ }
+ if (ptex->bind & PIPE_BIND_SCANOUT) {
+ surface->flags |= RADEON_SURF_SCANOUT;
}
- return h_align;
-}
-static unsigned r600_get_base_alignment(struct pipe_screen *screen,
- enum pipe_format format,
- unsigned array_mode)
-{
- struct r600_screen* rscreen = (struct r600_screen *)screen;
- unsigned pixsize = util_format_get_blocksize(format);
- int p_align = r600_get_block_alignment(screen, format, array_mode);
- int h_align = r600_get_height_alignment(screen, array_mode);
- int b_align;
+ if ((ptex->bind & PIPE_BIND_DEPTH_STENCIL) &&
+ !is_flushed_depth && is_depth) {
+ surface->flags |= RADEON_SURF_ZBUFFER;
- switch (array_mode) {
-#if 0
- case V_038000_ARRAY_2D_TILED_THIN1:
- b_align = MAX2(rscreen->tiling_info.num_banks * rscreen->tiling_info.num_channels * 8 * 8 * pixsize,
- p_align * pixsize * h_align);
- break;
- case V_038000_ARRAY_1D_TILED_THIN1:
- case V_038000_ARRAY_LINEAR_ALIGNED:
- case V_038000_ARRAY_LINEAR_GENERAL:
-#endif
- default:
- b_align = rscreen->tiling_info.group_bytes;
- break;
+ if (is_stencil) {
+ surface->flags |= RADEON_SURF_SBUFFER |
+ RADEON_SURF_HAS_SBUFFER_MIPTREE;
+ }
}
- return b_align;
+ return 0;
}
-static unsigned mip_minify(unsigned size, unsigned level)
+static int r600_setup_surface(struct pipe_screen *screen,
+ struct r600_resource_texture *rtex,
+ unsigned array_mode,
+ unsigned pitch_in_bytes_override)
{
- unsigned val;
- val = u_minify(size, level);
- if (level > 0)
- val = util_next_power_of_two(val);
- return val;
+ struct r600_screen *rscreen = (struct r600_screen*)screen;
+ int r;
+
+ r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
+ if (r) {
+ return r;
+ }
+ if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
+ /* old ddx on evergreen over estimate alignment for 1d, only 1 level
+ * for those
+ */
+ rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
+ rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
+ rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
+ if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
+ rtex->surface.stencil_offset =
+ rtex->surface.stencil_level[0].offset = rtex->surface.level[0].slice_size;
+ }
+ }
+ return 0;
}
-static unsigned r600_texture_get_nblocksx(struct pipe_screen *screen,
- struct r600_resource_texture *rtex,
- unsigned level)
+static boolean r600_texture_get_handle(struct pipe_screen* screen,
+ struct pipe_resource *ptex,
+ struct winsys_handle *whandle)
{
- struct pipe_resource *ptex = &rtex->resource.b.b;
- unsigned nblocksx, block_align, width;
- unsigned blocksize = util_format_get_blocksize(rtex->real_format);
-
- if (rtex->pitch_override)
- return rtex->pitch_override / blocksize;
+ struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
+ struct si_resource *resource = &rtex->resource;
+ struct radeon_surface *surface = &rtex->surface;
+ struct r600_screen *rscreen = (struct r600_screen*)screen;
- width = mip_minify(ptex->width0, level);
- nblocksx = util_format_get_nblocksx(rtex->real_format, width);
+ rscreen->ws->buffer_set_tiling(resource->buf,
+ NULL,
+ surface->level[0].mode >= RADEON_SURF_MODE_1D ?
+ RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
+ surface->level[0].mode >= RADEON_SURF_MODE_2D ?
+ RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
+ surface->bankw, surface->bankh,
+ surface->tile_split,
+ surface->stencil_tile_split,
+ surface->mtilea,
+ surface->level[0].pitch_bytes);
- block_align = r600_get_block_alignment(screen, rtex->real_format,
- rtex->array_mode[level]);
- nblocksx = align(nblocksx, block_align);
- return nblocksx;
+ return rscreen->ws->buffer_get_handle(resource->buf,
+ surface->level[0].pitch_bytes, whandle);
}
-static unsigned r600_texture_get_nblocksy(struct pipe_screen *screen,
- struct r600_resource_texture *rtex,
- unsigned level)
+static void r600_texture_destroy(struct pipe_screen *screen,
+ struct pipe_resource *ptex)
{
- struct pipe_resource *ptex = &rtex->resource.b.b;
- unsigned height, tile_height;
+ struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
+ struct si_resource *resource = &rtex->resource;
- height = mip_minify(ptex->height0, level);
- height = util_format_get_nblocksy(rtex->real_format, height);
- tile_height = r600_get_height_alignment(screen,
- rtex->array_mode[level]);
+ if (rtex->flushed_depth_texture)
+ si_resource_reference((struct si_resource **)&rtex->flushed_depth_texture, NULL);
- /* XXX Hack around an alignment issue. Less tests fail with this.
- *
- * The thing is depth-stencil buffers should be tiled, i.e.
- * the alignment should be >=8. If I make them tiled, stencil starts
- * working because it no longer overlaps with the depth buffer
- * in memory, but texturing like drawpix-stencil breaks. */
- if (util_format_is_depth_or_stencil(rtex->real_format) && tile_height < 8)
- tile_height = 8;
-
- height = align(height, tile_height);
- return height;
+ pb_reference(&resource->buf, NULL);
+ FREE(rtex);
}
-static void r600_texture_set_array_mode(struct pipe_screen *screen,
- struct r600_resource_texture *rtex,
- unsigned level, unsigned array_mode)
+static void *si_texture_transfer_map(struct pipe_context *ctx,
+ struct pipe_resource *texture,
+ unsigned level,
+ unsigned usage,
+ const struct pipe_box *box,
+ struct pipe_transfer **ptransfer)
{
- struct pipe_resource *ptex = &rtex->resource.b.b;
+ struct r600_context *rctx = (struct r600_context *)ctx;
+ struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
+ struct pipe_resource resource;
+ struct r600_transfer *trans;
+ boolean use_staging_texture = FALSE;
+ struct radeon_winsys_cs_handle *buf;
+ enum pipe_format format = texture->format;
+ unsigned offset = 0;
+ char *map;
- switch (array_mode) {
-#if 0
- case V_0280A0_ARRAY_LINEAR_GENERAL:
- case V_0280A0_ARRAY_LINEAR_ALIGNED:
- case V_0280A0_ARRAY_1D_TILED_THIN1:
-#endif
- default:
- rtex->array_mode[level] = array_mode;
- break;
-#if 0
- case V_0280A0_ARRAY_2D_TILED_THIN1:
- {
- unsigned w, h, tile_height, tile_width;
-
- tile_height = r600_get_height_alignment(screen, array_mode);
- tile_width = r600_get_block_alignment(screen, rtex->real_format, array_mode);
-
- w = mip_minify(ptex->width0, level);
- h = mip_minify(ptex->height0, level);
- if (w <= tile_width || h <= tile_height)
- rtex->array_mode[level] = V_0280A0_ARRAY_1D_TILED_THIN1;
- else
- rtex->array_mode[level] = array_mode;
- }
- break;
-#endif
- }
-}
+ /* We cannot map a tiled texture directly because the data is
+ * in a different order, therefore we do detiling using a blit.
+ *
+ * Also, use a temporary in GTT memory for read transfers, as
+ * the CPU is much happier reading out of cached system memory
+ * than uncached VRAM.
+ */
+ if (rtex->surface.level[level].mode != RADEON_SURF_MODE_LINEAR_ALIGNED &&
+ rtex->surface.level[level].mode != RADEON_SURF_MODE_LINEAR)
+ use_staging_texture = TRUE;
-static void r600_setup_miptree(struct pipe_screen *screen,
- struct r600_resource_texture *rtex,
- unsigned array_mode)
-{
- struct pipe_resource *ptex = &rtex->resource.b.b;
- enum chip_class chipc = ((struct r600_screen*)screen)->chip_class;
- unsigned size, layer_size, i, offset;
- unsigned nblocksx, nblocksy;
+ /* XXX: Use a staging texture for uploads if the underlying BO
+ * is busy. No interface for checking that currently? so do
+ * it eagerly whenever the transfer doesn't require a readback
+ * and might block.
+ */
+ if ((usage & PIPE_TRANSFER_WRITE) &&
+ !(usage & (PIPE_TRANSFER_READ |
+ PIPE_TRANSFER_DONTBLOCK |
+ PIPE_TRANSFER_UNSYNCHRONIZED)))
+ use_staging_texture = TRUE;
- for (i = 0, offset = 0; i <= ptex->last_level; i++) {
- unsigned blocksize = util_format_get_blocksize(rtex->real_format);
- unsigned base_align = r600_get_base_alignment(screen, rtex->real_format, array_mode);
+ if (texture->flags & R600_RESOURCE_FLAG_TRANSFER)
+ use_staging_texture = FALSE;
- r600_texture_set_array_mode(screen, rtex, i, array_mode);
+ if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY))
+ return NULL;
- nblocksx = r600_texture_get_nblocksx(screen, rtex, i);
- nblocksy = r600_texture_get_nblocksy(screen, rtex, i);
+ trans = CALLOC_STRUCT(r600_transfer);
+ if (trans == NULL)
+ return NULL;
+ pipe_resource_reference(&trans->transfer.resource, texture);
+ trans->transfer.level = level;
+ trans->transfer.usage = usage;
+ trans->transfer.box = *box;
+ if (rtex->is_depth) {
+ /* XXX: only readback the rectangle which is being mapped?
+ */
+ /* XXX: when discard is true, no need to read back from depth texture
+ */
+ struct r600_resource_texture *staging_depth;
- if (chipc >= CAYMAN /*&& array_mode == V_038000_ARRAY_LINEAR_GENERAL*/)
- layer_size = align(nblocksx, 64) * nblocksy * blocksize;
- else
- layer_size = nblocksx * nblocksy * blocksize;
+ if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
+ R600_ERR("failed to create temporary texture to hold untiled copy\n");
+ pipe_resource_reference(&trans->transfer.resource, NULL);
+ FREE(trans);
+ return NULL;
+ }
+ si_blit_uncompress_depth(ctx, rtex, staging_depth,
+ level, level,
+ box->z, box->z + box->depth - 1);
+ trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes;
+ trans->offset = r600_texture_get_offset(staging_depth, level, box->z);
- if (ptex->target == PIPE_TEXTURE_CUBE) {
- if (chipc >= CAYMAN)
- size = layer_size * 8;
+ trans->staging = &staging_depth->resource.b.b;
+ } else if (use_staging_texture) {
+ resource.target = PIPE_TEXTURE_2D;
+ resource.format = texture->format;
+ resource.width0 = box->width;
+ resource.height0 = box->height;
+ resource.depth0 = 1;
+ resource.array_size = 1;
+ resource.last_level = 0;
+ resource.nr_samples = 0;
+ resource.usage = PIPE_USAGE_STAGING;
+ resource.bind = 0;
+ resource.flags = R600_RESOURCE_FLAG_TRANSFER;
+ /* For texture reading, the temporary (detiled) texture is used as
+ * a render target when blitting from a tiled texture. */
+ if (usage & PIPE_TRANSFER_READ) {
+ resource.bind |= PIPE_BIND_RENDER_TARGET;
+ }
+ /* For texture writing, the temporary texture is used as a sampler
+ * when blitting into a tiled texture. */
+ if (usage & PIPE_TRANSFER_WRITE) {
+ resource.bind |= PIPE_BIND_SAMPLER_VIEW;
}
- else if (ptex->target == PIPE_TEXTURE_3D)
- size = layer_size * u_minify(ptex->depth0, i);
- else
- size = layer_size * ptex->array_size;
-
- /* align base image and start of miptree */
- if ((i == 0) || (i == 1))
- offset = align(offset, base_align);
- rtex->offset[i] = offset;
- rtex->layer_size[i] = layer_size;
- rtex->pitch_in_blocks[i] = nblocksx; /* CB talks in elements */
- rtex->pitch_in_bytes[i] = nblocksx * blocksize;
-
- offset += size;
+ /* Create the temporary texture. */
+ trans->staging = ctx->screen->resource_create(ctx->screen, &resource);
+ if (trans->staging == NULL) {
+ R600_ERR("failed to create temporary texture to hold untiled copy\n");
+ pipe_resource_reference(&trans->transfer.resource, NULL);
+ FREE(trans);
+ return NULL;
+ }
+
+ trans->transfer.stride = ((struct r600_resource_texture *)trans->staging)
+ ->surface.level[0].pitch_bytes;
+ if (usage & PIPE_TRANSFER_READ) {
+ r600_copy_to_staging_texture(ctx, trans);
+ /* Always referenced in the blit. */
+ radeonsi_flush(ctx, NULL, 0);
+ }
+ } else {
+ trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
+ trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
+ trans->offset = r600_texture_get_offset(rtex, level, box->z);
}
- rtex->size = offset;
-}
-/* Figure out whether u_blitter will fallback to a transfer operation.
- * If so, don't use a staging resource.
- */
-static boolean permit_hardware_blit(struct pipe_screen *screen,
- const struct pipe_resource *res)
-{
- unsigned bind;
+ if (trans->staging) {
+ buf = si_resource(trans->staging)->cs_buf;
+ } else {
+ buf = si_resource(trans->transfer.resource)->cs_buf;
+ }
- if (util_format_is_depth_or_stencil(res->format))
- bind = PIPE_BIND_DEPTH_STENCIL;
- else
- bind = PIPE_BIND_RENDER_TARGET;
-
- /* hackaround for S3TC */
- if (util_format_is_compressed(res->format))
- return TRUE;
-
- if (!screen->is_format_supported(screen,
- res->format,
- res->target,
- res->nr_samples,
- bind))
- return FALSE;
-
- if (!screen->is_format_supported(screen,
- res->format,
- res->target,
- res->nr_samples,
- PIPE_BIND_SAMPLER_VIEW))
- return FALSE;
-
- switch (res->usage) {
- case PIPE_USAGE_STREAM:
- case PIPE_USAGE_STAGING:
- return FALSE;
+ if (rtex->is_depth || !trans->staging)
+ offset = trans->offset +
+ box->y / util_format_get_blockheight(format) * trans->transfer.stride +
+ box->x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
- default:
- return TRUE;
+ if (!(map = rctx->ws->buffer_map(buf, rctx->cs, usage))) {
+ pipe_resource_reference(&trans->staging, NULL);
+ pipe_resource_reference(&trans->transfer.resource, NULL);
+ FREE(trans);
+ return NULL;
}
-}
-
-static boolean r600_texture_get_handle(struct pipe_screen* screen,
- struct pipe_resource *ptex,
- struct winsys_handle *whandle)
-{
- struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
- struct r600_resource *resource = &rtex->resource;
- struct r600_screen *rscreen = (struct r600_screen*)screen;
- return rscreen->ws->buffer_get_handle(resource->buf,
- rtex->pitch_in_bytes[0], whandle);
+ *ptransfer = &trans->transfer;
+ return map + offset;
}
-static void r600_texture_destroy(struct pipe_screen *screen,
- struct pipe_resource *ptex)
+static void si_texture_transfer_unmap(struct pipe_context *ctx,
+ struct pipe_transfer* transfer)
{
- struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
- struct r600_resource *resource = &rtex->resource;
+ struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
+ struct r600_context *rctx = (struct r600_context*)ctx;
+ struct radeon_winsys_cs_handle *buf;
+ struct pipe_resource *texture = transfer->resource;
+ struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
- if (rtex->flushed_depth_texture)
- pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
+ if (rtransfer->staging) {
+ buf = si_resource(rtransfer->staging)->cs_buf;
+ } else {
+ buf = si_resource(transfer->resource)->cs_buf;
+ }
+ rctx->ws->buffer_unmap(buf);
+
+ if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
+ if (rtex->is_depth) {
+ ctx->resource_copy_region(ctx, texture, transfer->level,
+ transfer->box.x, transfer->box.y, transfer->box.z,
+ &si_resource(rtransfer->staging)->b.b, transfer->level,
+ &transfer->box);
+ } else {
+ r600_copy_from_staging_texture(ctx, rtransfer);
+ }
+ }
- if (rtex->stencil)
- pipe_resource_reference((struct pipe_resource **)&rtex->stencil, NULL);
+ if (rtransfer->staging)
+ pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
- pb_reference(&resource->buf, NULL);
- FREE(rtex);
+ pipe_resource_reference(&transfer->resource, NULL);
+ FREE(transfer);
}
static const struct u_resource_vtbl r600_texture_vtbl =
{
r600_texture_get_handle, /* get_handle */
r600_texture_destroy, /* resource_destroy */
- r600_texture_get_transfer, /* get_transfer */
- r600_texture_transfer_destroy, /* transfer_destroy */
- r600_texture_transfer_map, /* transfer_map */
+ si_texture_transfer_map, /* transfer_map */
u_default_transfer_flush_region,/* transfer_flush_region */
- r600_texture_transfer_unmap, /* transfer_unmap */
- u_default_transfer_inline_write /* transfer_inline_write */
+ si_texture_transfer_unmap, /* transfer_unmap */
+ NULL /* transfer_inline_write */
};
+DEBUG_GET_ONCE_BOOL_OPTION(print_texdepth, "RADEON_PRINT_TEXDEPTH", FALSE);
+
static struct r600_resource_texture *
r600_texture_create_object(struct pipe_screen *screen,
const struct pipe_resource *base,
unsigned pitch_in_bytes_override,
unsigned max_buffer_size,
struct pb_buffer *buf,
- boolean alloc_bo)
+ boolean alloc_bo,
+ struct radeon_surface *surface)
{
struct r600_resource_texture *rtex;
- struct r600_resource *resource;
+ struct si_resource *resource;
struct r600_screen *rscreen = (struct r600_screen*)screen;
+ int r;
rtex = CALLOC_STRUCT(r600_resource_texture);
if (rtex == NULL)
rtex->pitch_override = pitch_in_bytes_override;
rtex->real_format = base->format;
- /* We must split depth and stencil into two separate buffers on Evergreen. */
- if (!(base->flags & R600_RESOURCE_FLAG_TRANSFER) &&
- ((struct r600_screen*)screen)->chip_class >= CAYMAN &&
- util_format_is_depth_and_stencil(base->format)) {
- struct pipe_resource stencil;
- unsigned stencil_pitch_override = 0;
-
- switch (base->format) {
- case PIPE_FORMAT_Z24_UNORM_S8_UINT:
- rtex->real_format = PIPE_FORMAT_Z24X8_UNORM;
- break;
- case PIPE_FORMAT_S8_UINT_Z24_UNORM:
- rtex->real_format = PIPE_FORMAT_X8Z24_UNORM;
- break;
- case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
- rtex->real_format = PIPE_FORMAT_Z32_FLOAT;
- break;
- default:
- assert(0);
- FREE(rtex);
- return NULL;
- }
-
- /* Divide the pitch in bytes by 4 for stencil, because it has a smaller pixel size. */
- if (pitch_in_bytes_override) {
- assert(base->format == PIPE_FORMAT_Z24_UNORM_S8_UINT ||
- base->format == PIPE_FORMAT_S8_UINT_Z24_UNORM);
- stencil_pitch_override = pitch_in_bytes_override / 4;
- }
-
- /* Allocate the stencil buffer. */
- stencil = *base;
- stencil.format = PIPE_FORMAT_S8_UINT;
- rtex->stencil = r600_texture_create_object(screen, &stencil, array_mode,
- stencil_pitch_override,
- max_buffer_size, NULL, FALSE);
- if (!rtex->stencil) {
- FREE(rtex);
- return NULL;
- }
- /* Proceed in creating the depth buffer. */
- }
-
- /* only mark depth textures the HW can hit as depth textures */
- if (util_format_is_depth_or_stencil(rtex->real_format) && permit_hardware_blit(screen, base))
- rtex->depth = 1;
-
- r600_setup_miptree(screen, rtex, array_mode);
-
- /* If we initialized separate stencil for Evergreen. place it after depth. */
- if (rtex->stencil) {
- unsigned stencil_align, stencil_offset;
+ /* don't include stencil-only formats which we don't support for rendering */
+ rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
- stencil_align = r600_get_base_alignment(screen, rtex->stencil->real_format, array_mode);
- stencil_offset = align(rtex->size, stencil_align);
-
- for (unsigned i = 0; i <= rtex->stencil->resource.b.b.last_level; i++)
- rtex->stencil->offset[i] += stencil_offset;
-
- rtex->size = stencil_offset + rtex->stencil->size;
+ rtex->surface = *surface;
+ r = r600_setup_surface(screen, rtex, array_mode, pitch_in_bytes_override);
+ if (r) {
+ FREE(rtex);
+ return NULL;
}
/* Now create the backing buffer. */
if (!buf && alloc_bo) {
- struct pipe_resource *ptex = &rtex->resource.b.b;
- unsigned base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
+ unsigned base_align = rtex->surface.bo_alignment;
+ unsigned size = rtex->surface.bo_size;
- if (!r600_init_resource(rscreen, resource, rtex->size, base_align, base->bind, base->usage)) {
- pipe_resource_reference((struct pipe_resource**)&rtex->stencil, NULL);
+ base_align = rtex->surface.bo_alignment;
+ if (!si_init_resource(rscreen, resource, size, base_align, FALSE, base->usage)) {
FREE(rtex);
return NULL;
}
resource->domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM;
}
- if (rtex->stencil) {
- pb_reference(&rtex->stencil->resource.buf, rtex->resource.buf);
- rtex->stencil->resource.cs_buf = rtex->resource.cs_buf;
- rtex->stencil->resource.domains = rtex->resource.domains;
+ if (debug_get_option_print_texdepth() && rtex->is_depth) {
+ printf("Texture: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
+ "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
+ "bpe=%u, nsamples=%u, flags=%u\n",
+ rtex->surface.npix_x, rtex->surface.npix_y,
+ rtex->surface.npix_z, rtex->surface.blk_w,
+ rtex->surface.blk_h, rtex->surface.blk_d,
+ rtex->surface.array_size, rtex->surface.last_level,
+ rtex->surface.bpe, rtex->surface.nsamples,
+ rtex->surface.flags);
+ if (rtex->surface.flags & RADEON_SURF_ZBUFFER) {
+ for (int i = 0; i <= rtex->surface.last_level; i++) {
+ printf(" Z %i: offset=%llu, slice_size=%llu, npix_x=%u, "
+ "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
+ "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
+ i, rtex->surface.level[i].offset,
+ rtex->surface.level[i].slice_size,
+ rtex->surface.level[i].npix_x,
+ rtex->surface.level[i].npix_y,
+ rtex->surface.level[i].npix_z,
+ rtex->surface.level[i].nblk_x,
+ rtex->surface.level[i].nblk_y,
+ rtex->surface.level[i].nblk_z,
+ rtex->surface.level[i].pitch_bytes,
+ rtex->surface.level[i].mode);
+ }
+ }
+ if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
+ for (int i = 0; i <= rtex->surface.last_level; i++) {
+ printf(" S %i: offset=%llu, slice_size=%llu, npix_x=%u, "
+ "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
+ "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
+ i, rtex->surface.stencil_level[i].offset,
+ rtex->surface.stencil_level[i].slice_size,
+ rtex->surface.stencil_level[i].npix_x,
+ rtex->surface.stencil_level[i].npix_y,
+ rtex->surface.stencil_level[i].npix_z,
+ rtex->surface.stencil_level[i].nblk_x,
+ rtex->surface.stencil_level[i].nblk_y,
+ rtex->surface.stencil_level[i].nblk_z,
+ rtex->surface.stencil_level[i].pitch_bytes,
+ rtex->surface.stencil_level[i].mode);
+ }
+ }
}
return rtex;
}
-DEBUG_GET_ONCE_BOOL_OPTION(tiling_enabled, "R600_TILING", FALSE);
-
-struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
- const struct pipe_resource *templ)
+struct pipe_resource *si_texture_create(struct pipe_screen *screen,
+ const struct pipe_resource *templ)
{
struct r600_screen *rscreen = (struct r600_screen*)screen;
- unsigned array_mode = 0;
+ struct radeon_surface surface;
+ unsigned array_mode = V_009910_ARRAY_LINEAR_ALIGNED;
+ int r;
if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
!(templ->bind & PIPE_BIND_SCANOUT)) {
-#if 0
- if (util_format_is_compressed(templ->format)) {
- array_mode = V_038000_ARRAY_1D_TILED_THIN1;
- }
- else if (debug_get_option_tiling_enabled() &&
- rscreen->info.drm_minor >= 9 &&
- permit_hardware_blit(screen, templ)) {
- array_mode = V_038000_ARRAY_2D_TILED_THIN1;
- }
-#endif
+ array_mode = V_009910_ARRAY_1D_TILED_THIN1;
}
+ r = r600_init_surface(rscreen, &surface, templ, array_mode,
+ templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
+ if (r) {
+ return NULL;
+ }
+ r = rscreen->ws->surface_best(rscreen->ws, &surface);
+ if (r) {
+ return NULL;
+ }
return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
- 0, 0, NULL, TRUE);
+ 0, 0, NULL, TRUE, &surface);
}
static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
pipe_resource_reference(&surface->base.texture, texture);
surface->base.context = pipe;
surface->base.format = surf_tmpl->format;
- surface->base.width = mip_minify(texture->width0, level);
- surface->base.height = mip_minify(texture->height0, level);
- surface->base.usage = surf_tmpl->usage;
+ surface->base.width = rtex->surface.level[level].npix_x;
+ surface->base.height = rtex->surface.level[level].npix_y;
surface->base.texture = texture;
surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
surface->base.u.tex.level = level;
- surface->aligned_height = r600_texture_get_nblocksy(pipe->screen,
- rtex, level);
return &surface->base;
}
FREE(surface);
}
-struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
- const struct pipe_resource *templ,
- struct winsys_handle *whandle)
+struct pipe_resource *si_texture_from_handle(struct pipe_screen *screen,
+ const struct pipe_resource *templ,
+ struct winsys_handle *whandle)
{
struct r600_screen *rscreen = (struct r600_screen*)screen;
struct pb_buffer *buf = NULL;
unsigned stride = 0;
- unsigned array_mode = 0;
+ unsigned array_mode = V_009910_ARRAY_LINEAR_ALIGNED;
enum radeon_bo_layout micro, macro;
+ struct radeon_surface surface;
+ int r;
/* Support only 2D textures without mipmaps */
if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
if (!buf)
return NULL;
- rscreen->ws->buffer_get_tiling(buf, µ, ¯o, NULL, NULL, NULL, NULL, NULL);
+ rscreen->ws->buffer_get_tiling(buf, µ, ¯o,
+ &surface.bankw, &surface.bankh,
+ &surface.tile_split,
+ &surface.stencil_tile_split,
+ &surface.mtilea);
-#if 0
if (macro == RADEON_LAYOUT_TILED)
- array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
+ array_mode = V_009910_ARRAY_2D_TILED_THIN1;
else if (micro == RADEON_LAYOUT_TILED)
- array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
+ array_mode = V_009910_ARRAY_1D_TILED_THIN1;
else
-#endif
- array_mode = 0;
+ array_mode = V_009910_ARRAY_LINEAR_ALIGNED;
+ r = r600_init_surface(rscreen, &surface, templ, array_mode, false);
+ if (r) {
+ return NULL;
+ }
return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
- stride, 0, buf, FALSE);
+ stride, 0, buf, FALSE, &surface);
}
-int r600_texture_depth_flush(struct pipe_context *ctx,
- struct pipe_resource *texture, boolean just_create)
+bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
+ struct pipe_resource *texture,
+ struct r600_resource_texture **staging)
{
struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
struct pipe_resource resource;
+ struct r600_resource_texture **flushed_depth_texture = staging ?
+ staging : &rtex->flushed_depth_texture;
- if (rtex->flushed_depth_texture)
- goto out;
+ if (!staging && rtex->flushed_depth_texture)
+ return true; /* it's ready */
resource.target = texture->target;
resource.format = texture->format;
resource.array_size = texture->array_size;
resource.last_level = texture->last_level;
resource.nr_samples = texture->nr_samples;
- resource.usage = PIPE_USAGE_DYNAMIC;
- resource.bind = texture->bind | PIPE_BIND_DEPTH_STENCIL;
- resource.flags = R600_RESOURCE_FLAG_TRANSFER | texture->flags;
-
- rtex->flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource);
- if (rtex->flushed_depth_texture == NULL) {
- R600_ERR("failed to create temporary texture to hold untiled copy\n");
- return -ENOMEM;
- }
-
- ((struct r600_resource_texture *)rtex->flushed_depth_texture)->is_flushing_texture = TRUE;
-out:
- if (just_create)
- return 0;
-
- /* XXX: only do this if the depth texture has actually changed:
- */
- r600_blit_uncompress_depth(ctx, rtex);
- return 0;
-}
-
-/* Needs adjustment for pixelformat:
- */
-static INLINE unsigned u_box_volume( const struct pipe_box *box )
-{
- return box->width * box->depth * box->height;
-};
-
-struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
- struct pipe_resource *texture,
- unsigned level,
- unsigned usage,
- const struct pipe_box *box)
-{
- struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
- struct pipe_resource resource;
- struct r600_transfer *trans;
- int r;
- boolean use_staging_texture = FALSE;
-
-#if 0
- /* We cannot map a tiled texture directly because the data is
- * in a different order, therefore we do detiling using a blit.
- *
- * Also, use a temporary in GTT memory for read transfers, as
- * the CPU is much happier reading out of cached system memory
- * than uncached VRAM.
- */
- if (R600_TEX_IS_TILED(rtex, level))
- use_staging_texture = TRUE;
-#endif
-
- if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024)
- use_staging_texture = TRUE;
-
- /* XXX: Use a staging texture for uploads if the underlying BO
- * is busy. No interface for checking that currently? so do
- * it eagerly whenever the transfer doesn't require a readback
- * and might block.
- */
- if ((usage & PIPE_TRANSFER_WRITE) &&
- !(usage & (PIPE_TRANSFER_READ |
- PIPE_TRANSFER_DONTBLOCK |
- PIPE_TRANSFER_UNSYNCHRONIZED)))
- use_staging_texture = TRUE;
-
- if (!permit_hardware_blit(ctx->screen, texture) ||
- (texture->flags & R600_RESOURCE_FLAG_TRANSFER))
- use_staging_texture = FALSE;
-
- if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY))
- return NULL;
-
- trans = CALLOC_STRUCT(r600_transfer);
- if (trans == NULL)
- return NULL;
- pipe_resource_reference(&trans->transfer.resource, texture);
- trans->transfer.level = level;
- trans->transfer.usage = usage;
- trans->transfer.box = *box;
- if (rtex->depth) {
- /* XXX: only readback the rectangle which is being mapped?
- */
- /* XXX: when discard is true, no need to read back from depth texture
- */
- r = r600_texture_depth_flush(ctx, texture, FALSE);
- if (r < 0) {
- R600_ERR("failed to create temporary texture to hold untiled copy\n");
- pipe_resource_reference(&trans->transfer.resource, NULL);
- FREE(trans);
- return NULL;
- }
- trans->transfer.stride = rtex->flushed_depth_texture->pitch_in_bytes[level];
- trans->offset = r600_texture_get_offset(rtex->flushed_depth_texture, level, box->z);
- return &trans->transfer;
- } else if (use_staging_texture) {
- resource.target = PIPE_TEXTURE_2D;
- resource.format = texture->format;
- resource.width0 = box->width;
- resource.height0 = box->height;
- resource.depth0 = 1;
- resource.array_size = 1;
- resource.last_level = 0;
- resource.nr_samples = 0;
- resource.usage = PIPE_USAGE_STAGING;
- resource.bind = 0;
- resource.flags = R600_RESOURCE_FLAG_TRANSFER;
- /* For texture reading, the temporary (detiled) texture is used as
- * a render target when blitting from a tiled texture. */
- if (usage & PIPE_TRANSFER_READ) {
- resource.bind |= PIPE_BIND_RENDER_TARGET;
- }
- /* For texture writing, the temporary texture is used as a sampler
- * when blitting into a tiled texture. */
- if (usage & PIPE_TRANSFER_WRITE) {
- resource.bind |= PIPE_BIND_SAMPLER_VIEW;
- }
- /* Create the temporary texture. */
- trans->staging_texture = ctx->screen->resource_create(ctx->screen, &resource);
- if (trans->staging_texture == NULL) {
- R600_ERR("failed to create temporary texture to hold untiled copy\n");
- pipe_resource_reference(&trans->transfer.resource, NULL);
- FREE(trans);
- return NULL;
- }
+ resource.usage = staging ? PIPE_USAGE_DYNAMIC : PIPE_USAGE_DEFAULT;
+ resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
+ resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
- trans->transfer.stride =
- ((struct r600_resource_texture *)trans->staging_texture)->pitch_in_bytes[0];
- if (usage & PIPE_TRANSFER_READ) {
- r600_copy_to_staging_texture(ctx, trans);
- /* Always referenced in the blit. */
- radeonsi_flush(ctx, NULL, 0);
- }
- return &trans->transfer;
- }
- trans->transfer.stride = rtex->pitch_in_bytes[level];
- trans->transfer.layer_stride = rtex->layer_size[level];
- trans->offset = r600_texture_get_offset(rtex, level, box->z);
- return &trans->transfer;
-}
-
-void r600_texture_transfer_destroy(struct pipe_context *ctx,
- struct pipe_transfer *transfer)
-{
- struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
- struct pipe_resource *texture = transfer->resource;
- struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
-
- if (rtransfer->staging_texture) {
- if (transfer->usage & PIPE_TRANSFER_WRITE) {
- r600_copy_from_staging_texture(ctx, rtransfer);
- }
- pipe_resource_reference(&rtransfer->staging_texture, NULL);
- }
-
- if (rtex->depth && !rtex->is_flushing_texture) {
- if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtex->flushed_depth_texture)
- r600_blit_push_depth(ctx, rtex);
- }
-
- pipe_resource_reference(&transfer->resource, NULL);
- FREE(transfer);
-}
-
-void* r600_texture_transfer_map(struct pipe_context *ctx,
- struct pipe_transfer* transfer)
-{
- struct r600_context *rctx = (struct r600_context *)ctx;
- struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
- struct radeon_winsys_cs_handle *buf;
- enum pipe_format format = transfer->resource->format;
- unsigned offset = 0;
- char *map;
-
- if (rtransfer->staging_texture) {
- buf = ((struct r600_resource *)rtransfer->staging_texture)->cs_buf;
- } else {
- struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
-
- if (rtex->flushed_depth_texture)
- buf = ((struct r600_resource *)rtex->flushed_depth_texture)->cs_buf;
- else
- buf = ((struct r600_resource *)transfer->resource)->cs_buf;
+ if (staging)
+ resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
+ else
+ rtex->dirty_db_mask = (1 << (resource.last_level+1)) - 1;
- offset = rtransfer->offset +
- transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
- transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
+ *flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource);
+ if (*flushed_depth_texture == NULL) {
+ R600_ERR("failed to create temporary texture to hold flushed depth\n");
+ return false;
}
- if (!(map = rctx->ws->buffer_map(buf, rctx->cs, transfer->usage))) {
- return NULL;
- }
-
- return map + offset;
-}
-
-void r600_texture_transfer_unmap(struct pipe_context *ctx,
- struct pipe_transfer* transfer)
-{
- struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
- struct r600_context *rctx = (struct r600_context*)ctx;
- struct radeon_winsys_cs_handle *buf;
-
- if (rtransfer->staging_texture) {
- buf = ((struct r600_resource *)rtransfer->staging_texture)->cs_buf;
- } else {
- struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
-
- if (rtex->flushed_depth_texture) {
- buf = ((struct r600_resource *)rtex->flushed_depth_texture)->cs_buf;
- } else {
- buf = ((struct r600_resource *)transfer->resource)->cs_buf;
- }
- }
- rctx->ws->buffer_unmap(buf);
+ (*flushed_depth_texture)->is_flushing_texture = TRUE;
+ return true;
}
-void r600_init_surface_functions(struct r600_context *r600)
+void si_init_surface_functions(struct r600_context *r600)
{
r600->context.create_surface = r600_create_surface;
r600->context.surface_destroy = r600_surface_destroy;
projects / mesa.git / blobdiff